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DS26528 Octal T1/E1/J1 Transceiver
www.maxim-ic.com
GENERAL DESCRIPTION
The DS26528 is a single-chip 8-port framer and line interface unit (LIU) combination for T1, E1, and J1 applications. Each port is independently configurable, supporting both long-haul and short-haul lines.
FEATURES

Eight Complete T1, E1, or J1 Long-Haul/ShortHaul Transceivers (LIU plus Framer) Independent T1, E1, or J1 Selections for Each Transceiver Internal Software-Selectable Transmit- and Receive-Side Termination for 100W T1 Twisted Pair, 110W J1 Twisted Pair, 120W E1 Twisted Pair, and 75W E1 Coaxial Applications Crystal-Less Jitter Attenuators can be Selected for Transmit or Receive Path. The Jitter Attenuator meets ETSI CTR 12/13, ITU G.736, G.742, G.823, and AT&T PUB 62411. External Master Clock can be Multiple of 2.048MHz or 1.544MHz for T1/J1 or E1 operation. This Clock is Internally Adapted for T1 or E1 Usage in the Host Mode. Receive Signal Level Indication from -2.5dB to -36dB in T1 Mode and -2.5dB to -44dB in E1 Mode in Approximate 2.5dB Increments Transmit Open and Short Circuit Detection LIU LOS in Accordance with G.775, ETSI 300233, and T1.231 Transmit Synchronizer Flexible Signaling Extraction and Insertion Using Either the System Interface or Microprocessor Port Alarm Detection and Insertion T1 Framing Formats of D4, SLC-96, and ESF J1 Support E1 G.704 and CRC-4 Multiframe T1 to E1 Conversion
APPLICATIONS
Routers Channel Service Units (CSUs) Data Service Units (DSUs) Muxes Switches Channel Banks T1/E1 Test Equipment
FUNCTIONAL DIAGRAM
T1/E1/J1 NETWORK

DS26528
T1/J1/E1 Transceiver
x8
BACKPLANE
TDM
Features continued in Section 2.
ORDERING INFORMATION
PART DS26528 TEMP RANGE -40C to +85C PIN-PACKAGE 256 TE-CSBGA
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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DS26528 Octal T1/E1/J1 Transceiver
TABLE OF CONTENTS
1. 2.
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
DETAILED DESCRIPTION.................................................................................................8 FEATURE HIGHLIGHTS ....................................................................................................9
GENERAL..................................................................................................................................... 9 LINE INTERFACE ........................................................................................................................... 9 CLOCK SYNTHESIZER ................................................................................................................... 9 JITTER ATTENUATOR .................................................................................................................... 9 FRAMER/FORMATTER ................................................................................................................... 9 SYSTEM INTERFACE ................................................................................................................... 10 HDLC CONTROLLERS ................................................................................................................ 10 TEST AND DIAGNOSTICS ............................................................................................................. 11 CONTROL PORT ......................................................................................................................... 11
3. 4. 5. 6. 7. 8.
8.1
APPLICATIONS ...............................................................................................................11 SPECIFICATIONS COMPLIANCE ...................................................................................12 ACRONYMS AND GLOSSARY .......................................................................................14 MAJOR OPERATING MODES.........................................................................................15 BLOCK DIAGRAMS.........................................................................................................15 PIN DESCRIPTIONS ........................................................................................................17
PIN FUNCTIONAL DESCRIPTION ................................................................................................... 17
9.
9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8
FUNCTIONAL DESCRIPTION .........................................................................................24
PROCESSOR INTERFACE ............................................................................................................. 24 CLOCK STRUCTURE.................................................................................................................... 24 RESETS AND POWER-DOWN MODES ........................................................................................... 26 INITIALIZATION AND CONFIGURATION ........................................................................................... 27 GLOBAL RESOURCES.................................................................................................................. 27 PER-PORT RESOURCES.............................................................................................................. 27 DEVICE INTERRUPTS .................................................................................................................. 28 SYSTEM BACKPLANE INTERFACE ................................................................................................. 30
Elastic Stores ....................................................................................................................................... 30 IBO Multiplexer..................................................................................................................................... 33 H.100 (CT-Bus) Compatibility .............................................................................................................. 40 Transmit and Receive Channel Blocking Registers............................................................................. 41 Transmit Fractional Support (Gapped Clock Mode) ............................................................................ 41 Receive Fractional Support (Gapped Clock Mode) ............................................................................. 41 T1 Framing ........................................................................................................................................... 42 E1 Framing........................................................................................................................................... 45 T1 Transmit Synchronizer .................................................................................................................... 47 Signaling .............................................................................................................................................. 48 T1 Datalink ........................................................................................................................................... 53 E1 Datalink ........................................................................................................................................... 55 Maintenance and Alarms ..................................................................................................................... 56 E1 Automatic Alarm Generation .......................................................................................................... 59 Error Count Registers .......................................................................................................................... 60 DS0 Monitoring Function...................................................................................................................... 62 Transmit Per-Channel Idle Code Insertion........................................................................................... 63 Receive Per-Channel Idle Code Insertion............................................................................................ 63 Per-Channel Loopback ........................................................................................................................ 63 E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only) ................................................................... 63 T1 Programmable In-Band Loop Code Generator............................................................................... 64 2 of 269
9.8.1 9.8.2 9.8.3 9.8.4 9.8.5 9.8.6
9.9
FRAMERS................................................................................................................................... 42
9.9.1 9.9.2 9.9.3 9.9.4 9.9.5 9.9.6 9.9.7 9.9.8 9.9.9 9.9.10 9.9.11 9.9.12 9.9.13 9.9.14 9.9.15
DS26528 Octal T1/E1/J1 Transceiver 9.9.16 Framer Payload Loopbacks ................................................................................................................. 66
9.10
9.10.1 9.10.2 9.10.3 9.10.4
HDLC CONTROLLERS ............................................................................................................. 67
Receive HDLC Controller..................................................................................................................... 67 Transmit HDLC Controller.................................................................................................................... 70 FIFO Information .................................................................................................................................. 70 HDLC Transmit Example ..................................................................................................................... 70
9.11
9.11.1 9.11.2 9.11.3 9.11.4 9.11.5
LINE INTERFACE UNITS (LIU) ................................................................................................... 72
LIU Operation....................................................................................................................................... 75 Transmitter ........................................................................................................................................... 76 Receiver ............................................................................................................................................... 79 Jitter Attenuator.................................................................................................................................... 81 LIU Loopbacks ..................................................................................................................................... 83
9.12
9.12.1 9.12.2
BIT ERROR RATE TEST FUNCTION (BERT) ............................................................................... 86
BERT Repetitive Pattern Set ............................................................................................................... 87 BERT Error Counter............................................................................................................................. 87
10.
DEVICE REGISTERS .......................................................................................................88
REGISTER LISTINGS ................................................................................................................ 88
Global Register List.............................................................................................................................. 90 Framer Register List............................................................................................................................. 90 LIU and BERT Register List ................................................................................................................. 97 10.1.1 10.1.2 10.1.3
10.1
10.2
10.2.1 10.2.2 10.2.3 10.2.4
REGISTER BIT MAPS ............................................................................................................... 98
Global Register Bit Map ....................................................................................................................... 98 Framer Register Bit Map ...................................................................................................................... 99 LIU Register Bit Map .......................................................................................................................... 105 BERT Register Bit Map ...................................................................................................................... 106
10.3 10.4
10.4.1 10.4.2
GLOBAL REGISTER DEFINITIONS ............................................................................................ 107 FRAMER REGISTER DEFINITIONS............................................................................................ 121
Receive Register Definitions .............................................................................................................. 121 Transmit Register Definitions ............................................................................................................. 179
10.5 10.6
LIU REGISTER DEFINITIONS................................................................................................... 214 BERT REGISTER DEFINITIONS............................................................................................... 223 T1 RECEIVER FUNCTIONAL TIMING DIAGRAMS ........................................................................ 231 T1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS .................................................................. 236 E1 RECEIVER FUNCTIONAL TIMING DIAGRAMS........................................................................ 241 E1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS .................................................................. 243 LINE INTERFACE CHARACTERISTICS ....................................................................................... 247 MICROPROCESSOR BUS AC CHARACTERISTICS...................................................................... 248 JTAG INTERFACE TIMING ...................................................................................................... 257 SYSTEM CLOCK AC CHARACTERISTICS .................................................................................. 258 INSTRUCTION REGISTER ........................................................................................................ 263 JTAG ID CODES................................................................................................................... 264 TEST REGISTERS .................................................................................................................. 264 BOUNDARY SCAN REGISTER.................................................................................................. 264 BYPASS REGISTER ................................................................................................................ 264 IDENTIFICATION REGISTER..................................................................................................... 264
11.
FUNCTIONAL TIMING ...................................................................................................231
11.1 11.2 11.3 11.4
12. 13.
OPERATING PARAMETERS.........................................................................................246 AC TIMING CHARACTERISTICS ..................................................................................248
12.1 13.1 13.2 13.3
14.
JTAG-BOUNDARY SCAN AND TEST ACCESS PORT................................................259
14.1 14.2 14.3 14.4 14.5 14.6
15. 16.
DOCUMENT REVISION HISTORY ................................................................................268 PACKAGE INFORMATION............................................................................................269
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LIST OF FIGURES
Figure 7-1. Block Diagram ..................................................................................................................... 15 Figure 7-2. Detailed Block Diagram ....................................................................................................... 16 Figure 8-1. BGA Pinout ......................................................................................................................... 23 Figure 9-1. Backplane Clock Generation ............................................................................................... 25 Figure 9-2. Device Interrupt Information Flow Diagram.......................................................................... 29 Figure 9-3. IBO Multiplexer Equivalent Circuit--4.096MHz.................................................................... 34 Figure 9-4. IBO Multiplexer Equivalent Circuit--8.192MHz.................................................................... 35 Figure 9-5. IBO Multiplexer Equivalent Circuit--16.384MHz.................................................................. 36 Figure 9-6. RSYNC Input In H.100 (Ct-Bus) Mode ................................................................................ 40 Figure 9-7. TSSYNCIO(Input Mode) Input In H.100 (CT-Bus) Mode...................................................... 41 Figure 9-8. CRC-4 Recalculate Method ................................................................................................. 63 Figure 9-9. Receive HDLC Example...................................................................................................... 69 Figure 9-10. HDLC Message Transmit Example.................................................................................... 71 Figure 9-11. Basic Balanced Network Connections ............................................................................... 73 Figure 9-12. Recommended Supply Decoupling.................................................................................... 75 Figure 9-13. T1/J1 Transmit Pulse Templates ....................................................................................... 77 Figure 9-14. E1 Transmit Pulse Templates............................................................................................ 78 Figure 9-15. Typical Monitor Application................................................................................................ 80 Figure 9-16. Jitter Attenuation ............................................................................................................... 83 Figure 9-17. Analog Loopback............................................................................................................... 83 Figure 9-18. Local Loopback ................................................................................................................. 84 Figure 9-19. Remote Loopback ............................................................................................................. 84 Figure 9-20. Dual Loopback .................................................................................................................. 85 Figure 10-1. Register Memory Map for the DS26528............................................................................. 89 Figure 11-1. T1 Receive Side D4 Timing ............................................................................................. 231 Figure 11-2. T1 Receive Side ESF Timing........................................................................................... 231 Figure 11-3. T1 Receive Side Boundary Timing (elastic store disabled) .............................................. 232 Figure 11-4. T1 Receive Side 1.544MHz Boundary Timing (e-store enabled)...................................... 232 Figure 11-5. T1 Receive Side 2.048MHz Boundary Timing (e-store enabled)...................................... 233 Figure 11-6. T1 Receive Side Interleave Bus Operation, BYTE Mode ................................................. 234 Figure 11-7. T1 Receive Side Interleave Bus Operation, FRAME Mode .............................................. 235 Figure 11-8. T1 Transmit Side D4 Timing ............................................................................................ 236 Figure 11-9. T1 Transmit Side ESF Timing.......................................................................................... 236 Figure 11-10. T1 Transmit Side Boundary Timing (e-store disabled) ................................................... 237 Figure 11-11. T1 Transmit Side 1.544MHz Boundary Timing (e-store enabled)................................... 237 Figure 11-12. T1 Transmit Side 2.048MHz Boundary Timing (e-store enabled)................................... 238 Figure 11-13. T1 Transmit Side Interleave Bus Operation, BYTE Mode .............................................. 239 Figure 11-14. T1 Transmit Interleave Bus Operation, FRAME Mode ................................................... 240 Figure 11-15. E1 Receive Side Timing ................................................................................................ 241 Figure 11-16. E1 Receive Side Boundary Timing (elastic store disabled) ............................................ 241 Figure 11-17. E1 Receive Side 1.544MHz Boundary Timing (e-store enabled) ................................... 242 Figure 11-18. E1 Receive Side 2.048MHz Boundary Timing (e-store enabled) ................................... 242 Figure 11-19. E1 Transmit Side Timing ............................................................................................... 243 Figure 11-20. E1 Transmit Side Boundary Timing (elastic store disabled) ........................................... 243 Figure 11-21. E1 Transmit Side 1.544MHz Boundary Timing (e-store enabled) .................................. 244 Figure 11-22. E1 Transmit Side 2.048MHz Boundary Timing (e-store enabled) .................................. 244 Figure 11-23. E1 G.802 Timing ........................................................................................................... 245 Figure 13-1. Intel Bus Read Timing (BTS = 0) ..................................................................................... 249 Figure 13-2. Intel Bus Write Timing (BTS = 0) ..................................................................................... 249 Figure 13-3. Motorola Bus Read Timing (BTS = 1) .............................................................................. 250 Figure 13-4. Motorola Bus Write Timing (BTS = 1) .............................................................................. 250
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Figure 13-5. Receive Framer Timing--Backplane (T1 Mode) .............................................................. 252 Figure 13-6. Receive Side Timing, Elastic Store Enabled (T1 Mode)................................................... 253 Figure 13-7. Receive Framer Timing--Line Side ................................................................................. 253 Figure 13-8. Transmit Formatter Timing--Backplane .......................................................................... 255 Figure 13-9. Transmit Formatter Timing, Elastic Store Enabled........................................................... 256 Figure 13-10. Transmit Formatter Timing--Line Side .......................................................................... 256 Figure 13-11. JTAG Interface Timing Diagram .................................................................................... 257 Figure 14-1. JTAG Functional Block Diagram...................................................................................... 259 Figure 14-2. Tap Controller State Diagram .......................................................................................... 262
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LIST OF TABLES
Table 4-1. T1-Related Telecommunications Specifications.................................................................... 12 Table 4-2. E1-Related Telecommunications Specifications ................................................................... 13 Table 8-1. Detailed Pin Descriptions...................................................................................................... 17 Table 9-1. Reset Functions.................................................................................................................... 26 Table 9-2. Registers Related to the Elastic Store .................................................................................. 30 Table 9-3. Elastic Store Delay After Initialization ................................................................................... 31 Table 9-4. Registers related to the IBO Multiplexer ............................................................................... 33 Table 9-5. RSER Output Pin Definitions ................................................................................................ 37 Table 9-6. RSIG Output Pin Definitions ................................................................................................. 37 Table 9-7. TSER Input Pin Definitions ................................................................................................... 38 Table 9-8. TSIG Input Pin Definitions..................................................................................................... 38 Table 9-9. RSYNC Input Pin Definitions ................................................................................................ 39 Table 9-10. D4 Framing Mode ............................................................................................................... 43 Table 9-11. ESF Framing Mode............................................................................................................. 43 Table 9-12. SLC-96 Framing ................................................................................................................. 44 Table 9-13. E1 FAS/NFAS Framing....................................................................................................... 45 Table 9-14. Registers Related to Setting Up the Framer ....................................................................... 46 Table 9-15. Registers Related to the Transmit Synchronizer ................................................................. 47 Table 9-16. Registers Related to Signaling............................................................................................ 48 Table 9-17. Registers Related to SLC96 ............................................................................................... 51 Table 9-18. Registers Related to T1 Transmit BOC............................................................................... 53 Table 9-19. Registers Related to T1 Receive BOC................................................................................ 53 Table 9-20. Registers Related to T1 Transmit FDL................................................................................ 54 Table 9-21. Registers Related to T1 Receive FDL................................................................................. 55 Table 9-22. Registers Related to Maintenance and Alarms ................................................................... 57 Table 9-23. T1 Alarm Criteria ................................................................................................................ 59 Table 9-24. T1 Line Code Violation Counting Options ........................................................................... 60 Table 9-25. E1 Line Code Violation Counting Options ........................................................................... 61 Table 9-26. T1 Path Code Violation Counting Arrangements................................................................. 61 Table 9-27. T1 Frames Out Of Sync Counting Arrangements................................................................ 62 Table 9-28. Registers Related to DS0 Monitoring.................................................................................. 62 Table 9-29. Registers Related to T1 In-Band Loop Code Generator...................................................... 64 Table 9-30. Registers Related to T1 In-Band Loop Code Detection....................................................... 65 Table 9-31. Register Related to Framer Payload Loopbacks................................................................. 66 Table 9-32. Registers Related to Control of DS26528 LIU..................................................................... 75 Table 9-33. The Telecommunications Specification Compliance for DS26528 Transmitters.................. 76 Table 9-34. Transformer Specifications ................................................................................................. 76 Table 9-35. T1.231, G.775, and ETSI 300 233 Loss Criteria Specifications........................................... 80 Table 9-36. Jitter Attenuator Standards Compliance.............................................................................. 82 Table 10-1. Register Address Ranges (in Hex)...................................................................................... 88 Table 10-2. Global Register List ............................................................................................................ 90 Table 10-3. Framer Register List ........................................................................................................... 90 Table 10-4. LIU Register List ................................................................................................................. 97 Table 10-5. BERT Register List ............................................................................................................. 97 Table 10-6. Global Register Bit Map...................................................................................................... 98 Table 10-7. Framer Register Bit Map..................................................................................................... 99 Table 10-8. LIU Register Bit Map......................................................................................................... 105 Table 10-9. BERT Register Bit Map..................................................................................................... 106 Table 10-10. Backplane Reference Clock Select................................................................................. 110 Table 10-11. Master Clock Input Selection .......................................................................................... 111 Table 10-12. Device ID Codes in this Product Family .......................................................................... 114
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Table 10-13. LIU Register Set ............................................................................................................. 214 Table 10-14. Transmit Load Impedance Selection............................................................................... 215 Table 10-15. Transmit Pulse Shape Selection ..................................................................................... 215 Table 10-16. Receive Level Indication ................................................................................................. 220 Table 10-17. Receive Impedance Selection ........................................................................................ 221 Table 10-18. Receiver Sensitivity Selection with Monitor Mode Disabled ............................................ 222 Table 10-19. Receiver Sensitivity Selection with Monitor Mode Enabled ............................................. 222 Table 10-20. BERT Register Set ......................................................................................................... 223 Table 10-21. BERT Pattern Select....................................................................................................... 225 Table 10-22. BERT Error Insertion Rate .............................................................................................. 226 Table 10-23. BERT Repetitive Pattern Length Select .......................................................................... 226 Table 12-1. Transmitter Characteristics ............................................................................................... 247 Table 12-2. Reciever Characteristics................................................................................................... 247 Table 13-1. AC Characteristics -Microprocessor Bus Timing .............................................................. 248 Table 13-2. Receiver AC Characteristics ............................................................................................. 251 Table 13-3. Transmit AC Characteristics ............................................................................................. 254 Table 14-1. Instruction Codes for IEEE 1149.1 Architecture ................................................................ 263 Table 14-2. ID Code Structure............................................................................................................. 264 Table 14-3. Boundary Scan Control Bits.............................................................................................. 264
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1. DETAILED DESCRIPTION
The DS26528 is an 8-port monolithic device featuring independent transceivers that can be software configured for T1, E1, or J1 operation. Each transceiver is composed of a line interface unit, framer, HDLC controller, elastic store, and a TDM backplane interface. The DS26528 is controlled via an 8-bit parallel port. Internal impedance matching is provided for both transmit and receive paths, reducing external component count. The LIU is composed of a transmit interface, receive interface, and a jitter attenuator. The transmit interface is responsible for generating the necessary waveshapes for driving the network and providing the correct source impedance depending on the type of media used. T1 waveform generation includes DSX-1 line build-outs as well as CSU line build-outs of 0dB, -7.5dB, -15dB, and -22.5dB. E1 waveform generation includes G.703 waveshapes for both 75W coax and 120W twisted cables. The receive interface provides network termination and recovers clock and data from the network. The receive sensitivity adjusts automatically to the incoming signal level and can be programmed for 0dB to -43dB or 0dB to -12dB for E1 applications and 0dB to -15dB or 0dB to -36dB for T1 applications. The jitter attenuator removes phase jitter from the transmitted or received signal. The crystal-less jitter attenuator requires only a T1 or E1 clock rate, or multiple thereof, for both E1 and T1 applications, and can be placed in either transmit or receive data paths. On the transmit side, clock, data, and frame-sync signals are provided to the framer by the backplane interface section. The framer inserts the appropriate synchronization framing patterns, alarm information, calculates and inserts the CRC codes, and provides the B8ZS/HDB3 (zero code suppression) and AMI line coding. The receiveside framer decodes AMI, B8ZS, and HDB3 line coding, synchronizes to the data stream, reports alarm information, counts framing/coding/CRC errors, and provides clock, data, and frame-sync signals to the backplane interface section. Both transmit and receive paths have access to an HDLC controller. The HDLC controller transmits and receives data via the framer block. The HDLC controller can be assigned to any time slot, a portion of a time slot or to FDL (T1) or Sa bits (E1). Each controller has 64-byte FIFOs, reducing the amount of processor overhead required to manage the flow of data. The backplane interface provides a versatile method of sending and receiving data from the host system. Elastic stores provide a method for interfacing to asynchronous systems, converting from a T1/E1 network to a 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz, or N x 64kHz system backplane. The elastic stores also manage slip conditions (asynchronous interface). An interleave bus option (IBO) is provided to allow up to eight transceivers (single DS26528) to share a high-speed backplane. The DS26528 also contains an internal clock adapter useful for the creation of a synchronous, high-frequency backplane timing source. The parallel port provides access for configuration and status of all the DS26528's features. Diagnostic capabilities include loopbacks, PRBS pattern generation/detection, and 16-bit loop-up and loop-down code generation and detection.
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2. FEATURE HIGHLIGHTS
2.1

General
17mm x 17mm, 256-pin TE-CSBGA (1.00mm pitch) 3.3V supply with 5V tolerant inputs and outputs IEEE 1149.1 JTAG boundary scan Development support will include evaluation kit, driver source code, and reference designs
2.2

Line Interface
Requires a single master clock (MCLK) for both E1 and T1 operation. Master clock can be 1.544MHz, 2.048MHz, 3.088MHz, 4.096MHz, 6.276MHz, 8.192MHz, 12.552MHz, or 16.384MHz. Fully software configurable Short- and long-haul applications Ranges include 0dB to -43dB, 0dB to -30dB, 0dB to 20dB, and 0dB to -12dB for E1; 0dB to -36dB, 0dB to 30dB, 0dB to 20dB, and 0dB to -15dB for T1 Receiver signal level indication from -2.5dB to -36dB in T1 mode and -2.5dB to -44dB in E1 mode in 2.5dB increments Internal receive termination option for 75, 100W, 110W, and 120W lines Monitor application gain settings of 14dB, 20dB, 26dB, and 32dB G.703 receive synchronization signal mode Flexible transmit waveform generation T1 DSX-1 line build-outs T1 CSU line build-outs of 0dB, -7.5dB, -15dB, and -22.5dB E1 waveforms include G.703 waveshapes for both 75W coax and 120W twisted cables Analog loss of signal detection AIS generation independent of loopbacks Alternating ones and zeros generation Receiver power-down Transmitter power-down Transmitter short-circuit limiter with current limit exceeded indication Transmit open-circuit-detected indication
2.3

Clock Synthesizer
Output frequencies include 2.048MHz, 4.096MHz, 8.192MHz, and 16.384MHz Derived from user selected recovered receive clock
2.4

Jitter Attenuator
32-bit or 128-bit crystal-less jitter attenuator Requires only a 1.544MHz or 2.048MHz master clock or multiple thereof, for both E1 and T1 operation Can be placed in either the receive or transmit path or disabled Limit trip indication
2.5

Framer/Formatter
Fully independent transmit and receive functionality Full receive and transmit path transparency T1 framing formats D4 and ESF per T1.403, and expanded SLC-96 support (TR-TSY-008). E1 FAS framing and CRC-4 multiframe per G.704/G.706, and G.732 CAS multiframe Transmit side synchronizer Transmit midpath CRC recalculate (E1) Detailed alarm and status reporting with optional interrupt support 9 of 269
DS26528 Octal T1/E1/J1 Transceiver Large path and line error counters - T1:- BPV, CV, CRC6, and framing bit errors - E1: BPV, CV, CRC4, E-bit, and frame alignment errors - Timed or manual update modes DS1 Idle Code Generation on a per-channel basis in both transmit and receive paths - User defined - Digital Milliwatt ANSI T1.403-1999 Support G.965 V5.2 link detect Ability to monitor one DS0 channel in both the transmit and receive paths In-Band Repeating Pattern Generators and Detectors - Three independent Generators and Detectors - Patterns from 1 to 8 bits or 16 bits in Length Bit Oriented Code (BOC) support Flexible signaling support - Software or hardware based - Interrupt generated on change of signaling data - Optional receive signaling freeze on loss of frame, loss of signal, or frame slip - Hardware pins provided to indicate Loss of Frame (LOF), Loss of Signal (LOS), Loss of Transmit Clock (LOTC), or signaling freeze condition. Automatic RAI generation to ETS 300 011 specifications RAI-CI and AIS-CI support Expanded access to Sa and Si bits Option to extend carrier loss criteria to a 1ms period as per ETS 300 233 Japanese J1 support Ability to calculate and check CRC6 according to the Japanese standard Ability to generate Yellow Alarm according to the Japanese standard T1 to E1 conversion

2.6

System Interface
Independent two-frame receive and transmit elastic stores Independent control and clocking Controlled slip capability with status Minimum delay mode supported Flexible TDM backplane supports bus rates from 1.544MHz to 16.384MHz Supports T1 to CEPT (E1) conversion Programmable output clocks for fractional T1, E1, H0, and H12 applications Interleaving PCM bus operation Hardware signaling capability Receive signaling reinsertion to a backplane multiframe sync Availability of signaling in a separate PCM data stream Signaling freezing Ability to pass the T1 F-bit position through the elastic stores in the 2.048MHz backplane mode User-selectable synthesized clock output
2.7

HDLC Controllers
One HDLC controller engine for each T1/E1 port Independent 64-byte Rx and Tx buffers with interrupt support Access FDL, Sa, or single DS0 channel Compatible with polled or interrupt driven environments 10 of 269
DS26528 Octal T1/E1/J1 Transceiver
2.8

Test and Diagnostics
IEEE 1149.1 Support Per-channel programmable on-chip bit error-rate testing (BERT) Pseudorandom patterns including QRSS User-defined repetitive patterns Daly pattern Error insertion single and continuous Total-bit and errored-bit counts Payload error insertion Error insertion in the payload portion of the T1 frame in the transmit path Errors can be inserted over the entire frame or selected channels Insertion options include continuous and absolute number with selectable insertion rates F-bit corruption for line testing Loopbacks (remote, local, analog, and per-channel loopback)
2.9

Control Port
8-bit parallel control port Intel or Motorola nonmultiplexed support Flexible status registers support polled, interrupt, or hybrid program environments Software reset supported Hardware reset pin Software access to device ID and silicon revision
3. APPLICATIONS
The DS26528 is useful in applications such as: Routers Channel Service Units (CSUs) Data Service Units (DSUs) Muxes Switches Channel Banks T1/E1 Test Equipment
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4. SPECIFICATIONS COMPLIANCE
The DS26528 LIU meets all the latest relevant telecommunications specifications. Table 4-1 provides the T1 and E1 specifications and relevant sections that are applicable to the DS26528.
Table 4-1. T1-Related Telecommunications Specifications
ANSI T1.102- Digital Hierarchy Electrical Interface. AMI Coding. B8ZS Substitution Definition. DS1 Electrical Interface. Line rate +/- 32ppm; Pulse Amplitude between 2.4 to 3.6 V peak; Power Level between 12.6 to 17.9dbm; The T1 pulse mask is provided that we comply. DSX-1 for cross connects the return loss is greater than -26dB. The DSX-1 cable is restricted up to 655 feet. This specification also provides cable characteristics of DSX-Cross Connect cable ---22 AVG cables of 1000 feet. ANSI T1.231- Digital Hierarchy- Layer 1 in Service Performance Monitoring BPV Error Definition; Excessive Zero Definition; LOS description; AIS definition. ANSI T1.403- Network and Customer Installation Interface- DS1 Electrical Interface Description of the Measurement of the T1 Characteristics--100W. Pulse shape and template compliance according to T1.102; Power level 12.4 to 19.7dbm when all ones is transmitted. LBO for the Customer Interface (CI) is specified as 0dB, -7.5dB and -15dB. Line rate is +/-32 ppm. Pulse Amplitude is 2.4 to 3.6V. AIS generation as unframed all ones is defined. The total cable attenuation is defined as 22dB. The DS26528 will function with up to -36dB cable loss. Note that the pulse template defined by T1.403 and T1.102 are different --- specifically at Times .61, -.27, -34 and .77. The DS26528 is complaint to both templates. Pub 62411 This specification has tighter jitter tolerance and transfer characteristics than other specifications. The jitter transfer characteristics are tighter than G.736 and Jitter Tolerance is tighter the G.823. (ANSI) "Digital Hierarchy - Electrical Interfaces" (ANSI) "Digital Hierarchy - Formats Specification" (ANSI) "Digital Hierarchy - Layer 1 In-Service Digital Transmission Performance Monitoring" (ANSI) "Network and Customer Installation Interfaces - DS1 Electrical Interface" (AT&T) "Requirements for Interfacing Digital Terminal Equipment to Services Employing the Extended Super frame Format" (AT&T) "High Capacity Digital Service Channel Interface Specification" (TTC) "Frame Structures on Primary and Secondary Hierarchical Digital Interfaces" (TTC) "ISDN Primary Rate User-Network Interface Layer 1 Specification"
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DS26528 Octal T1/E1/J1 Transceiver
Table 4-2. E1-Related Telecommunications Specifications
ITUT G.703 Physical/Electrical Characteristics of G.703 Hierarchical Digital Interfaces Defines the 2048Kbit/s bit rate--2048 50ppm; The transmission media are 75W coax or 120W twisted pair; peak to peak space voltage is 0.237V; Nominal pulse width is 244 ns. Return loss 51 to 102Hz is 6dB, 102 to 3072 Hz is 8dB, 2048 to 3072 Hz is 14dB Nominal peak voltage is 2.37V for coax and 3V for twisted pair. The pulse template for E1 is defined in G.703. ITUT G.736 Characteristics of Synchronous Digital Multiplex Equipment operating at 2048Kbit/s The peak to peak jitter at 2048Kbit/s has to be less than 0.05 UI at 20 to 100Hz. Jitter transfer between 2.048 synchronization signal and 2.048 transmission signal is provided. ITUT G.742 Second Order Digital Multiplex Equipment Operating at 8448Kbit/s The DS26528 jitter attenuator is complaint with Jitter transfer curve for sinusoidal jitter input. ITUT G.772 This specification provides the method for using receiver for transceiver 0 as a monitor for the rest of the 7 transmitter/receiver combinations. ITUT G.775 A LOS detection criterion is defined. ITUT G.823 The control of jitter and wander within digital networks which are based on 2.048Kbit/s hierarchy G.823 provides the jitter amplitude tolerance at different frequencies, specifically 20Hz, 2.4kHz, 18kHz, and 100kHz. ETSI 300 233 This specification provides LOS and AIS signal criteria for E1 mode Pub 62411 This specification has tighter jitter tolerance and transfer characteristics than other specifications. The jitter transfer characteristics are tighter than G.736 and Jitter Tolerance is tighter then G.823. (ITU) "Synchronous Frame Structures used at 1544, 6312, 2048, 8488 and 44736Kbit/s Hierarchical Levels" (ITU) "Frame Alignment and Cyclic Redundancy Check (CRC) Procedures Relating to Basic Frame Structures Defined in Recommendation G.704" (ITU) "Characteristics of primary PCM Multiplex Equipment Operating at 2048Kbit/s" (ITU) Characteristics of a synchronous digital multiplex equipment operating at 2048Kbit/s" (ITU) "Loss Of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance Criteria" (ITU) "The Control of Jitter and Wander Within Digital Networks Which are Based on the 2048Kbit/s Hierarchy" (ITU) "Primary Rate User-Network Interface - Layer 1 Specification" (ITU) "Error Performance Measuring Equipment Operating at the Primary Rate and Above" (ITU) "In-service code violation monitors for digital systems" (ETSI) "Integrated Services Digital Network (ISDN); Primary rate User-Network Interface (UNI); Part 1/ Layer 1 specification" (ETSI) "Transmission and multiplexing; Physical/electrical characteristics of hierarchical digital interfaces for equipment using the 2048Kbit/s-based plesiochronous or synchronous digital hierarchies" (ETSI) "Integrated Services Digital Network (ISDN); Access digital section for ISDN primary rate" (ETSI) "Integrated Services Digital Network (ISDN); Attachment requirements for terminal equipment to connect to an ISDN using ISDN primary rate access" (ETSI) "Business Telecommunications (BT); Open Network Provision (ONP) technical requirements; 2048 Kbit/s digital unstructured leased lines (D2048U) attachment requirements for terminal equipment interface" (ETSI) "Business Telecommunications (BTC); 2048 Kbit/s digital structured leased lines (D2048S); Attachment requirements for terminal equipment interface" (ITU) "Synchronous Frame Structures used at 1544, 6312, 2048, 8488 and 44736Kbit/s Hierarchical Levels" (ITU) "Frame Alignment and Cyclic Redundancy Check (CRC) Procedures Relating to Basic Frame Structures Defined in Recommendation G.704"
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DS26528 Octal T1/E1/J1 Transceiver
5. ACRONYMS AND GLOSSARY
This data sheet assumes a particular nomenclature of the T1 and E1 operating environment. In each 125ms T1 frame, there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is sent first followed by channel 1. For T1 and E1 each channel is made up of 8 bits, which are numbered 1 to 8. Bit 1, the MSB, is transmitted first. Bit 8, the LSB, is transmitted last. Locked refers to two clock signals that are phase- or frequency-locked or derived from a common clock (i.e., a 1.544MHz clock can be locked to a 2.048MHz clock if they share the same 8kHz component).
TIME SLOT NUMBERING SCHEMES
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TS Channel 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Phone Channel
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DS26528 Octal T1/E1/J1 Transceiver
6. MAJOR OPERATING MODES
The DS26528 has two major modes of operation: T1 mode and E1 mode. The mode of operation for each LIU is configured in the LTRCR register. The mode of operation for each framer is configured in the TMMR register. J1 operation is a special case of T1 operating mode.
7. BLOCK DIAGRAMS
Figure 7-1. Block Diagram
DS26528
LIU #8 LIU #7 LIU #6 LIU #5 LIU #4 LIU #3 LIU #2 RTIP RRING TTIP TRING x8 LINE INTERFACE UNIT FRAMER #8 FRAMER #7 FRAMER #6 FRAMER #5 FRAMER #4 FRAMER #3 FRAMER #2 T1/E1 FRAMER HDLC BERT ELASTIC STORES INTERFACE #8 INTERFACE #7 INTERFACE #6 INTERFACE #5 INTERFACE #4 INTERFACE #3 INTERFACE #2 BACKPLANE INTERFACE RECEIVE BACKPLANE SIGNALS TRANSMIT BACKPLANE SIGNALS HARDWARE ALARM INDICATORS x8 MICRO PROCESSOR INTERFACE CLOCK GENERATION
JTAG PORT
CONTROLLER PORT
TEST PORT
CLOCK ADAPTER
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DS26528 Octal T1/E1/J1 Transceiver
Figure 7-3. Detailed Block Diagram
TRANSCEIVER #1 of 8:
Tx BERT Tx FRAMER:
Tx HDLC
Tx Signaling/ Channel Blocking
TTIPn ANALOG OUTPUTS TRINGn
TRANSMIT LIU JITTER ATTENUATOR
Waveform Shaper/Line Driver
B8ZS/ HDB3 Encode
TCLKn TSERn
TRANSMIT ENABLE
ALB
System IF
BACKPLANE INTERFACE
Elastic Store
TSYNCn TSSYNCIO (Input Mode) TSYSCLK RSYSCLK
LLB
FLB PLB RLB
RTIPn ANALOG INPUTS RRINGn
RECEIVE LIU
Clock/Data Recovery
Rx FRAMER:
System IF B8ZS/ HDB3 Decode Elastic Store
RSYNCn RSERn RCLKn Rx Signaling/ Channel Blocking
DS26528
Rx BERT
Rx HDLC
MICROPROCESSOR INTERFACE
JTAG PORT
RESET BLOCK
PRE-SCALER PLL
MCLK
BACKPLANE CLOCK GENERATOR
TSSYNCIO (Output Mode) BPCLK REFCLK
A[12:0] D[7:0] CSB RDB/DSB WRB/RWB BTS INTB
JTDO JTDI JTMS JTCLK JTRST
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RESETB
DS26528 Octal T1/E1/J1 Transceiver
8. PIN DESCRIPTIONS
8.1 Pin Functional Description Table 8-1. Detailed Pin Descriptions
NAME
ANALOG TRANSMIT
TTIP1 TTIP2 TTIP3 TTIP4 TTIP5 TTIP6 TTIP7 TTIP8 TRING1 TRING2 TRING3 TRING4 TRING5 TRING6 TRING7 TRING8 TXENABLE ANALOG RECEIVE RTIP1 RTIP2 RTIP3 RTIP4 RTIP5 RTIP6 RTIP7 RTIP8 RRING1 RRING2 RRING3 RRING4 RRING5 RRING6 RRING7 RRING8 TRANSMIT FRAMER TSER1 TSER2 TSER3 TSER4 TSER5 TSER6 TSER7 TSER8 TCLK1 TCLK2 TCLK3 TCLK4 TCLK5 TCLK6 TCLK7 C1 F1 L1 P1 P16 L16 F16 C16 C2 F2 L2 P2 P15 L15 F15 C15 F6 E7 R4 N7 M10 L11 F10 D12 C5 D7 P5 L8 L10 N11 E10 A1, A2 H1, H2 J1, J2 T1, T2 T15, T16 J15, J16 H15, H16 A15, A16 A3, B3 G3, H3 J3, K3 R3, T3 R14,T14 J14, K14 G14, H14 A14, B14 L13 I Transmit Bipolar Tip for Transceiver 1 to 8. These pins are differential line driver tip outputs. These pins can be High-Z if: Analog Output High-Z If pin TXENABLE is low the TTIP/TRING will be High-Z. Note that if TXENABLE is low, the register settings for control of the TTIP/TRING are ignored and output is High-Z. The differential outputs of TTIPn and TRINGn can provide internal matched impedance for E1 75W , E1 120W, T1 100W, or J1 110W. The user has the option of turning off internal termination. Note: The two pins shown for each Transmit Bipolar Tip (for example, Pins A1 and A2 for TTIP1) should be tied together. Transmit Bipolar Ring for Transceiver 1 to 8. These pins are differential line driver ring outputs. These pins can be High-Z if: Analog Output High-Z If pin TXENABLE is low the TTIP/TRING will be High-Z. Note that if TXENABLE is low, the register settings for control of the TTIP/TRING are ignored and output is High-Z. The differential outputs of TTIPn and TRINGn can provide internal matched impedance for E1 75W, E1 120W, T1 100W, or J1 110W. The user has the option of turning off internal termination. Note: The two pins shown for each Transmit Bipolar Ring (for example, Pins A3 and B3 for TRING1) should be tied together. Transmit Enable. If this pin is pulled low, all the transmitter outputs (TTIP and TRING) are High-Z. The register settings for tri-state control of TTIP/TRING are ignored if TXEnable is low. If TXEnable is high, the particular driver can be tri-stated by the register settings.
PIN
TYPE
DESCRIPTION
Analog Input
Receive Bipolar Tip for Transceiver 1 to 8. The differential inputs of RTIPn and RRINGn can provide internal matched impedance for E1 75W, E1 120W, T1 100W, or J1 110W. The user has the option of turning off internal termination via the LIU receive impedance and sensitivity monitor Register.
Analog Input
Receive Bipolar Ring for Transceiver 1 to 8. The differential inputs of RTIPn and RRINGn can provide internal matched impedance for E1 75W, E1 120W, T1 100W, or J1 110W. The user has the option of turning off internal termination via the LIU receive impedance and sensitivity monitor register.
I
Transmit NRZ Serial Data. Sampled on the falling edge of TCLK when the transmit side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled. In IBO Mode, data for multiple framers can be used in High Speed Multiplexed Scheme. This is described in Section 9.8.2. The table there presents the combination of framer data for each of the streams. TSYSCLK is used as a reference when IBO is invoked. See Table 9-7. Transmit Clock. A 1.544 MHz or a 2.048MHz primary clock. Used to clock data through the transmit side of the transceiver. TSER data is sampled on the falling edge of TCLK. TCLK is used to sample TSER when the elastic store is not enabled or IBO is not used.
I
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DS26528 Octal T1/E1/J1 Transceiver
NAME
TCLK8
PIN
B13
TYPE
DESCRIPTION
Transmit System Clock. 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz clock. Only used when the transmit-side elastic store function is enabled. Should be tied low in applications that do not use the transmit side elastic store. This is a common clock that is used for all 8 transmitters. The clock can be 4.096MHz, 8.912MHz, or 16.384MHz when IBO mode is used.
TSYSCLK
P13
I
TSYNC1 TSYNC2 TSYNC3 TSYNC4 TSYNC5 TSYNC6 TSYNC7 TSYNC8
B4 F7 M6 M7 N10 T12 B11 A13
IO
Transmit Synchronization. A pulse at this pin establishes either frame or multiframe boundaries for the transmit side. This signal can also be programmed to output either a frame or multiframe pulse. If this pin is set to output pulses at frame boundaries, it can also be set to output double-wide pulses at signaling frames in T1 mode. The operation of this signal is synchronous with TCLK. Transmit System Synchronization In. Only used when the transmit-side elastic store is enabled. A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Note that if the elastic store is enabled, frame or multiframe boundary will be established for all 8 transmitters. Should be tied low in applications that do not use the transmit side elastic store. The operation of this signal is synchronous with TSYSCLK.
TSSYNCIO
N13
I/O Transmit System Synchronization Out. If configured as an output, an 8kHz pulse synchronous to the BPCLK will be generated. This pulse in combination with Bpclk can be used as an IBO Master. The BPCLK can be sourced to RSYSCLK and TSYSCLK and TSSYNCIO as a source to RSYNC and TSSYNCIO of DS26528 or RSYNC and TSSYNC of other Dallas Semiconductor Parts.
TSIG1 TSIG2 TSIG3 TSIG4 TSIG5 TSIG6 TSIG7 TSIG8 TCHBLK/CLK1 TCHBLK/CLK2 TCHBLK/CLK3 TCHBLK/CLK4 TCHBLK/CLK5 TCHBLK/CLK6 TCHBLK/CLK7 TCHBLK/CLK8 RECEIVE FRAMER RSER1 RSER2 RSER3 RSER4 RSER5 RSER6 RSER7 RSER8 RCLK1 RCLK2 RCLK3 RCLK4 RCLK5 RCLK6 RCLK7
D5 A6 T4 R6 T10 R12 A11 C13 A5 C7 L7 P7 P9 P11 D10 E11 E5 D6 N4 N6 M11 M12 B12 F11 F4 G4 L4 M4 K13 J13 F13
I
Transmit Signaling. When enabled, this input samples signaling bits for insertion into outgoing PCM data stream. Sampled on the falling edge of TCLK when the transmit-side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit-side elastic store is enabled. In IBO mode, the TSIG streams can run up to 16.384MHz. See Table 9-8.
O
Transmit Channel Block or Transmit Channel Block Clock. A dual function pin. TCHBLK is a user programmable output that can be forced high or low during any of the channels. Synchronous with TCLK when the transmit side elastic store is disabled. Synchronous with TSYSCLK when the transmit side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD controller in applications where not all channels are used such as Fractional T1, Fractional E1, 384 KBPS (H0), 768 KBPS or ISDN-PRI. Also useful for locating individual channels in drop-and-insert applications, for external per-channel loopback, and for per-channel conditioning. TCHCLK. TCHCLK is a 192kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel. It can also be programmed to output a gated transmit bit clock controlled by TCHBLK. It is synchronous with TCLK when the transmit-side elastic store is disabled. It is synchronous with TSYSCLK when the transmit-side elastic store is enabled. Useful for parallel-to-serial conversion of channel data.
O
Received Serial Data. Received NRZ serial data. Updated on rising edges of RCLK when the receive side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled. When IBO mode is used, the RSER pins can output data for multiple framers. The RSER data is synchronous to RSYSCLK. This is described in Section 9.8.2 or see Table 9-5.
O
Receive Clock. A 1.544MHz (T1) or 2.048MHz (E1) clock that is used to clock data through the receive-side framer. This clock is recovered from the signal at RTIP and RRING. RSER data is output on the rising edge of RCLK. RCLK is used to output RSER when the elastic store is not enabled or IBO is not used. When the elastic store is enabled or IBO is used the RSER is clocked by RSYSCLK.
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DS26528 Octal T1/E1/J1 Transceiver
NAME
RCLK8 RSYSCLK
PIN
E13 L12
TYPE
DESCRIPTION
Receive System Clock. 1.544MHz, 2.048MHz, 4.096MHz, or 8.192MHz or 16.384MHz receive backplane clock. Only used when the receive side elastic store function is enabled. Should be tied low in applications that do not use the receive side elastic store. Multiple of 2.048MHz is expected when the IBO Mode is used. Note that RSYSCLK is used for all 8 transceivers. Receive Synchronization. If the receive side elastic store is enabled, then this signal is used to input a frame or multiframe boundary pulse if set to output frame boundaries then RSYNC can be programmed to output double-wide pulses on signaling frames in T1 mode. In E1 Mode RSYNC out can be used to indicate CAS and CRC4 Multiframe. The DS26528 also has the facility to accept H.100 compatible synchronization signal. The default direction of this pin at power up is Input as determined by the RSIO control bit in the RIOCR.2 register. Receive Multiframe or Frame Synchronization. A dual function pin to indicate Frame or Multiframe Synchronization. RFSYNC is an extracted 8 kHz pulse, one RCLK wide that identifies frame boundaries. RMSYNC is an extracted pulse, one RCLK wide (elastic store disabled) or one RSYSCLK wide (elastic store enabled), which identifies multiframe boundaries. When the receive elastic store is enabled, the RMSYNC signal indicates the multiframe sync on the system (backplane) side of the Elastic Store. In E1 mode, will indicate either the CRC4 or CAS multiframe as determined by the RSMS2 control bit in the RIOCR.1 register.
I
RSYNC1 RSYNC2 RSYNC3 RSYNC4 RSYNC5 RSYNC6 RSYNC7 RSYNC8 RM/RFSYNC1 RM/RFSYNC2 RM/RFSYNC3 RM/RFSYNC4 RM/RFSYNC5 RM/RFSYNC6 RM/RFSYNC7 RM/RFSYNC8 RSIG1 RSIG2 RSIG3 RSIG4 RSIG5 RSIG6 RSIG7 RSIG8 AL/RSIGF/ FLOS1 AL/RSIGF/ FLOS2 AL/RSIGF/ FLOS3 AL/RSIGF/ FLOS4 AL/RSIGF/ FLOS5 AL/RSIGF/ FLOS6 AL/RSIGF/ FLOS7 AL/RSIGF/ FLOS8 RLF/LTC1 RLF/LTC2 RLF/LTC3 RLF/LTC4 RLF/LTC5 RLF/LTC6 RLF/LTC7 RLF/LTC8
A4 B6 N5 T6 R10 P12 C11 D13 C4 C6 P4 P6 P10 N12 D11 E12 D4 E6 M5 R5 R11 R13 A12 F12 C3 F3 L3 P3
I/O
O
O
Receive Signaling. Outputs signaling bits in a PCM format. Updated on rising edges of RCLK when the receive side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled. See Table 9-6.
Analog Loss or Receive Signaling Freeze or Framer LOS. Analog LOS reflects the LOS (Loss of Signal) detected by the LIU front end and Framer LOS is LOS detection by the corresponding framer; the same pins can reflect Receive Signaling Freeze indications. This selection can be made by settings in Global Transceiver Control Register. O If Framer LOS is selected, this pin can be programmed to toggle high when the framer detects a loss of signal condition, or when the signaling data is frozen via either automatic or manual intervention. The indication is used to alert downstream equipment of the condition.
P14 L14 F14 C14 D3 E3 M3 N3 N14 M14 E14 D14 O
Receive Loss of Frame or Loss of Transmit Clock. This pin can also be programmed to either toggle high when the synchronizer is searching for the frame and multiframe or to toggle high if the TCLK pin has not been toggled for approximately three clock periods.
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DS26528 Octal T1/E1/J1 Transceiver
NAME
RCHBLK/CLK1 RCHBLK/CLK2 RCHBLK/CLK3 RCHBLK/CLK4 RCHBLK/CLK5 RCHBLK/CLK6 RCHBLK/CLK7 RCHBLK/CLK8
PIN
E4 B5 L6 T5 T11 T13 C12 G13
TYPE
DESCRIPTION
Receive Channel Block or Receive Channel Block Clock. Pin can be configured to output either RCHBLK or RCHCLK. RCHBLK is a user-programmable output that can be forced high or low during any of the 24 T1 or 32 E1 channels. Synchronous with RCLK when the receive side elastic store is disabled. Synchronous with RSYSCLK when the receive-side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD controller in applications where not all channels are used such as fractional service, 384kbps service, 768kbps, or ISDN-PRI. Also useful for locating individual channels in drop-and-insert applications, for external per-channel loopback, and for per-channel conditioning. RCHCLK is a 192 kHz (T1) or 256kHz (E1) clock that pulses high during the LSB of each channel. Synchronous with RCLK when the receive-side elastic store is disabled. Synchronous with RSYSCLK when the receive-side elastic store is enabled. Useful for parallel-to-serial conversion of channel data. Backplane Clock. Programmable clock output that can be set to 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz. The reference for this clock can be RCLK from any of the LIU, 1.544MHz or 2.048MHz frequency derived from MCLK or an external reference clock. This allows for the IBO clock to reference from external source or T1J1E1 recovered clock or the MCLK oscillator.
O
BPCLK
E8
O
MICROPROCESSOR INTERFACE A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 CSB C8 A8 B8 F8 B9 A9 C9 D9 E9 F9 B10 A10 C10 T9 N9 M9 R8 T8 P8 L9 N8 T7
I
Address12 to Address0. This bus selects a specific register in the DS26528 during read/write access. A12 is the MSB and A0 is the LSB.
I/O
Data7 to Data0. This 8-bit, bidirectional data bus is used for read/write access of the DS26528 information and control registers. D7 is the MSB and D0 is the LSB.
I
Chip Select Bar. This active-low signal is used to qualify register read/write accesses. The RDDSB and WRB signals are qualified with CSB. Read Bar Data or Strobe Bar. This active-low signal along with CSB qualifies read access to one of the DS26528 registers. The DS26528 drives the data bus with the contents of the addressed register while RDB and CSB are both low. Write Bar/Read-Write Bar. This active-low signal along with CSB qualifies write access to one of the DS26528 registers. Data at D[7/0] is written into the addressed register at the rising edge of WRB while CSB is low. Interrupt Bar. This active-low, open-drain output is asserted when an unmasked interrupt event is detected. INTB will be deasserted when all interrupts have been acknowledged and serviced. Extensive Mask bits are provided at the global level, framer, LIU, and BERT level. Bus Type Select. Set high to select Motorola bus timing, low to select Intel bus timing. This pin controls the function of the RDDSB, and WRB pins.
RDB/DSB
M8
I
WRB/RWB
R7
I
INTB BTS SYSTEM INTERFACE
R9 M13
U I
MCLK
B7
I
Master Clock. This is an independent free-running clock whose input can be a multiple of 2.048MHz 50ppm or 1.544MHz 50ppm. The clock selection is available by bits MPS0 and MPS1 and FREQSEL. Multiple of 2.048MHz can be internally adapted to 1.544MHz. Multiple of 1.544MHz can be adapted to 2.048MHz. Note that TCLK has to be 2.048MHz for E1 and 1.544MHz for T1/J1 operation. See Table 10-11.
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DS26528 Octal T1/E1/J1 Transceiver
NAME
RESETB
PIN
J12
TYPE
I
DESCRIPTION
Reset Bar. Active-low reset. This input forces the complete DS26528 reset. This includes reset of the registers, framers, and LIUs. Reference Clock Input/Output Input: A 2.048MHz or 1.544MHz clock input. This clock can be used to generate the backplane clock. This allows for the users to synchronize the system backplane with the reference clock. The other options for the backplane clock reference are LIU-received clocks or MCLK. Output: This signal can also be used to output a 1.544MHz or 2.048MHz reference clock. This allows for multiple DS26528 to share the same reference for generation of the backplane clock. Hence, in a system consisting of multiple DS26528s, one can be a master and others a slave using the same Reference Clock.
REFCLKIO
A7
I/O
TEST DIGIOEN D8 I Pullup Digital Enable. When this pin and JTRST are pulled low all Digital I/O pins are placed in a high-impedance state. If this pin is High the Digital I/O pins operate normally. This pin has to be connected to VDD for normal operation. JTAG Reset. JTRST is used to asynchronously reset the test access port controller. After power up, JTRST must be toggled from low to high. This action will set the device into the JTAG DEVICE ID mode. Pulling JTRST low restores normal device operation. JTRST is pulled HIGH internally via a 10kW resistor operation. If boundary scan is not used, this pin should be held low. JTAG Mode Select. This pin is sampled on the rising edge of JTCLK and is used to place the test access port into the various defined IEEE 1149.1 states. This pin has a 10k pull up resistor. JTAG Clock. This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. JTAG Data In. Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin has a 10kW pullup resistor. JTAG Data Out. Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin should be left unconnected.
JTRST
L5
I Pullup
JTMS
K4
I Pullup I I Pullup O High-Z
JTCLK JTDI JTDO POWER SUPPLIES ATVDD1 ATVDD2 ATVDD3 ATVDD4 ATVDD5 ATVDD6 ATVDD7 ATVDD8 ATVSS1 ATVSS2 ATVSS3 ATVSS4 ATVSS5 ATVSS6 ATVSS7 ATVSS8 ARVDD1 ARVDD2 ARVDD3 ARVDD4 ARVDD5 ARVDD6 ARVDD7 ARVDD8 ARVSS1 ARVSS2 ARVSS3 ARVSS4 ARVSS5 ARVSS6
F5 H4 J4
B1 G1 K1 R1 R16 K16 G16 B16 B2 G2 K2 R2 R15 K15 G15 B15 D1 E1 M1 N1 N16 M16 E16 D16 D2 E2 M2 N2 N15 M15
--
3.3V Analog Transmit Power Supply. These VDD inputs are used for the transmit LIU sections of the DS26528.
--
Analog Transmit VSS. These pins are used for transmit analog VSS.
--
3.3 V Analog Receive Power Supply. This VDD inputs are used for the Receive LIU sections of the DS26528.
--
Analog Receive VSS. These pins are used for analog VSS for the receivers.
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DS26528 Octal T1/E1/J1 Transceiver
NAME
ARVSS7 ARVSS8 ACVDD ACVSS DVDD DVDDIO DVSS DVSSIO
PIN
E15 D15 H7 J7 G5-G12, H8, H9 H5, H6, H10, H11 H12, H13, J8, J9, K5- K12 J5, J6, J10, J11
TYPE
DESCRIPTION
-- -- -- -- --- ---
Analog Clock Conversion VDD. This VDD inputs are used for the clock conversion unit of the DS26528. Analog Clock VSS. This pin is used for clock converter analog VSS. 3.3V Power Supply for Digital Framers 3.3V Power Supply for I/Os Digital Ground for the Framers Digital Ground for the I/Os
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DS26528 Octal T1/E1/J1 Transceiver
Figure 8-1. BGA Pinout
1 A B C D E F G H J K L M N P R T
TTIP1
2
TTIP1
3
TRING1
4
RSYNC1
5
TCHBLK1
6
TSIG2
7
REFCLKIO
8
A11
9
A7
10
A1
11
TSIG7
12
RSIG7
13
TSYNC8
14
TRING8
15
TTIP8
16
TTIP8
ATVDD1
ATVSS1
TRING1
TSYNC1
RCHBLK2
RSYNC2
MCLK
A10
A8
A2
TSYNC7
RSER7
TCLK8
TRING8
ATVSS8
ATVDD8
RTIP1
RRING1 ALRSIGF1 RMRFSYNC1
TCLK1
RMRFSYNC2 TCHBLK2
A12
A6
A0
RSYNC7
RCHBLK7
TSIG8
ALRSIGF8
RRING8
RTIP8
ARVDD1
ARVSS1
RLFLTC1
RSIG1
TSIG1
RSER2
TCLK2
DIGIOEN
A5
TCHBLK7
RMRFSYNC7
TSER8
RSYNC8
RLFLTC8
ARVSS8
ARVDD8
ARVDD2
ARVSS2
RLFLTC2
RCHBLK1
RSER1
RSIG2
TSER2
BPCLK
A4
TCLK7
TCHBLK8
RMFSYC8
RCLK8
RLFLTC7
ARVSS7
ARVDD7
RTIP2
RRING2 ALRSIGF2
RCLK1
JTCLK
TSER1
TSYNC2
A9
A3
TSER7
RSER8
RSIG8
RCLK7
ALRSIGF7
RRING7
RTIP7
ATVDD2
ATVSS2
TRING2
RCLK2
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
RCHBLK8
TRING7
ATVSS7
ATVDD7
TTIP2
TTIP2
TRING2
JTDI
DVDDIO
DVDDIO
ACVDD
DVDD
DVDD
DVDDIO
DVDDIO
DVSS
DVSS
TRING7
TTIP7
TTIP7
TTIP3
TTIP3
TRING3
JTDO
DVSSIO
DVSSIO
ACVSS
DVSS
DVSS
DVSSIO
DVSSIO
RESETB
RCLK6
TRING6
TTIP6
TTIP6
ATVDD3
ATVSS3
TRING3
JTMS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
RCLK5
TRING6
ATVSS6
ATVDD6
RTIP3
RRING3 ALRSIGF3
RCLK3
JTRST
RCHBLK3
TCHBLK3
TCLK4
D1
TCLK5
TSER6
RSYSCLK
TXENABLE
ALRSIGF6
RRING6
RTIP6
ARVDD3
ARVSS3
RLFLTC3
RCLK4
RSIG3
TSYNC3
TSYNC4
RDB/ DSB
D5
TSER5
RSER5
RSER6
BTS
RLFLTC6
ARVSS6
ARVDD6
ARVDD4
ARVSS4
RLFLTC4
RSER3
RSYNC3
RSER4
TSER4
D0
D6
TSYNC5
TCLK6
RMRFSYNC6 TSSYNCIO
RLFLTC5
ARVSS5
ARVDD5
RTIP4
RRING4 ALRSIGF4 RMRFSYNC3
TCLK3
RMRFSYNC4 TCHBLK4
D2
TCHBLK5 RMRFSYNC5
TCHBLK6
RSYNC6
TSYSCLK
ALRSIGF5
RRING5
RTIP5
ATVDD4
ATVSS4
TRING4
TSER3
RSIG4
TSIG4
WRB/ RWB
D4
INTB
RSYNC5
RSIG5
TSIG6
RSIG6
TRING5
ATVSS5
ATVDD5
TTIP4
TTIP4
TRING4
TSIG3
RCHBLK4
RSYNC4
CSB
D3
D7
TSIG5
RCHBLK5
TSYNC6
RCHBLK6
TRING5
TTIP5
TTIP5
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DS26528 Octal T1/E1/J1 Transceiver
9. FUNCTIONAL DESCRIPTION
9.1 Processor Interface
Microprocessor control of the DS26528 is accomplished through the 28 hardware pins of the microprocessor port. The 8-bit parallel data bus can be configured for Intel or Motorola modes of operation with the Bus Type Select (BTS) pin. When the BTS pin is a logic 0, bus timing is in Intel mode, as shown in Figure 13-1 and Figure 13-3. When the BTS pin is a logic 1, bus timing is in Motorola mode, as shown in Figure 13-5 and Figure 13-7. The address space is mapped through the use of 13 address lines, A0-A12. Multiplexed Mode is not supported on the processor interface. The Chip Select Bar (CSB) pin must be brought to a logic low level to gain read and write access to the microprocessor port. With Intel timing selected, the Read Bar (RDB) and Write Bar (WRB) pins are used to indicate read and write operations and latch data data through the interface. With Motorola timing selected, the Read-Write Bar (RWB) pin is used to indicate read and write operations while the Data Strobe Bar (DSB) pin is used to latch data through the interface. The interrupt output pin (INTB) is an open-drain output that will assert a logic-low level upon a number of software maskable interrupt conditions. This pin is normally connected to the microprocessor interrupt input. The device has a bulk write mode that allows a microprocessor to write all eight internal transceivers with each bus write cycle. By setting the BWE bit (GTCR1.2), each port write cycle will write to all eight framers, LIUs, or BERTs at the same time. The BWE bit must be cleared before normal write operation is resumed. This function is useful for device initialization. The register map is shown in Figure 10-1.
9.2
Clock Structure
The user should provide a system clock to the MCLK input of 2.048MHz, 1.544MHz, or a multiple of up to 8x the T1 and E1 frequencies. To meet many specifications, the MCLK source should have 50ppm accuracy.
9.2.1.1 Backplane Clock Generation
The DS26528 provides facility for provision of BPCLK at 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz (see Figure 9-1). The Global Transceiver Control Register (GTCCR ) is used to control the backplane clock generation. This register is also used to program REFCLKIO as an input or output. REFCLKIO can be an output sourcing MCLKT1 or MCLKE1 as shown in Figure 9-1. This backplane clock and frame pulse (TSSYNCIO) can be used by the DS26528 and other IBO equipped devices as an "IBO Bus Master." Hence the DS26528 will provide the 8 KHZ Sync Pulse and 4,8,16MHz clock. This can be used by the link layer devices and frames connected to the IBO Bus.
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DS26528 Octal T1/E1/J1 Transceiver
Figure 9-1. Backplane Clock Generation
BPREFSEL3:0
BPCLK1:0 RCLK1 RCLK2 RCLK3 RCLK4 RCLK5 RCLK6 RCLK7 RCLK8 MCLK Pre Scaler PLL MCLKT1 MCLKE1 REFCLKIO BFREQSEL
Clock Multiplexor
CLK GEN
BPCLK
TSSYNCIO REFCLKIO
The reference clock for the Backplane Clock generator can be: * * * * * External Master Clock. A pre-scaler can be used to generate T1 or E1 Frequency External Reference Clock REFCLKIO. This allows for multiple DS26528 to use the Backplane Clock from a common reference. Internal LIU recovered RCLKs 1 to 8. The Clock Generator can be used to generate BPCLK of 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz for the IBO. If MCLK or RCLKs are used as a reference, REFCLKIO can be used to provide a 2.048MHz or 1.544MHz clock for external use.
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DS26528 Octal T1/E1/J1 Transceiver
9.3
Resets and Power-Down Modes
A hardware reset is issued by forcing the RESETB pin to logic low. The RESETB input pin resets all framers, LIUs, and BERTs. Note that not all registers are cleared to 00h on a reset condition. The register space must be reinitialized to appropriate values after a hardware or software reset has occurred. This includes writing reserved locations to 00h.
Table 9-1. Reset Functions
RESET FUNCTION Hardware Device Reset Hardware JTAG Reset Global Framer and BERT Resets Global LIU Resets Framer Receive Reset Framer Transmit Reset HDLC Receive Reset HDLC Transmit Reset Elastic Store Receive Reset Elastic Store Transmit Reset Bit Oriented Code Receive Reset Loop Code Integration Reset LOCATION RESETB Pin JTRST Pin GFSRR.0 - .7 GLSRR.0 - .7 RMMR.1 TMMR.1 RHC.6 THC1.5 RESCR.2 TESCR.2 T1RBOCC.7 T1RDNCD1, T1RUPCD1 T1RSCD1 COMMENTS Transition to a logic 0 level resets the DS26528. Resets the JTAG test port. Writing to these bits resets the associated Framer and BERT (transmit & receive). Writing to these bits resets the associated Line Interface Unit. Writing to this bit resets the Receive Framer. Writing to this bit resets the Transmit Framer. Writing to this bit resets the Receive HDLC controller. Writing to this bit resets the Transmit HDLC controller. Writing to this bit resets the Receive Elastic Store. Writing to this bit resets the Transmit Elastic Store. Writing to this bit resets the Receive BOC controller. Writing to these registers resets the programmable in-band code integration period. Writing to this register resets the programmable in-band code integration period.
Spare Code Integration Reset
The DS26528 has several features included to reduce power consumption. The individual LIU transmitters can be powered down by setting the TPDE bit in the LIU maintenance control register (LMCR). Note that powering down the transmit LIU results in a High-Z state for the corresponding TTIP and TRING pins, and reduced operating current. The RPDE in the LMCR register can be used to power down the LIU receiver. The TE (Transmit Enable) bit in the LMCR register can be used to disable the TTIP and TRING outputs and place them in a high-impedance mode, while keeping the LIU in an active state (powered up). This is useful for equipment protection switching applications.
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DS26528 Octal T1/E1/J1 Transceiver
9.4
Initialization and Configuration
EXAMPLE DEVICE INITIALIZATION SEQUENCE: STEP 1: Reset the device by pulling the RESETB pin low, applying power to the device, or by using the software reset bits outlined in Section 9.3. Clear all reset bits. Allow time for the reset recovery. STEP 2: Check the Device ID in the IDR register STEP 3: Write the GTCCR register to correctly configure the system clocks. If supplying a 1.544MHz MCLK follows this write with at least a 300ns delay in order to allow the clock system to properly adjust. STEP 4: Write the entire remainder of the register space for each port with 00h, including reserved register locations. STEP 5: Choose T1/J1 or E1 operation for the framers by configuring the T1/E1 bit in the TMMR and RMMR registers for each framer. Set the FRM_EN bit to 1 in the TMMR and RMMR registers. If using Software Transmit Signaling in E1 mode, program the E1TAF and E1TNAF registers as required. Configure the framer Transmit Control Registers (TCR1 - TCR4). Configure the framer Receive Control Registers (RCR1 - RCR3). Configure other framer features as appropriate. STEP 6: Choose T1/J1 or E1 operation for the LIUs by configuring the T1J1E1S bit in the LTRCR register. Configure the Line Build Out for each LIU. Configure other LIU features as appropriate. Set the TE (Transmit Enable) bit to turn on the TTIP and TRING outputs. STEP 7: Configure the Elastic Stores, HDLC Controller, and BERT as needed. STEP 8: Set the INIT_DONE bit in the TMMR and RMMR registers for each framer.
9.5
Global Resources
All eight framers share a common microprocessor port. All ports share a common MCLK, and there is a common software configurable BPCLK output. A set of Global registers are located at 0F0h-0FFh and include Global resets, global interrupt status, interrupt masking, clock configuration, and the Device ID registers. See the Global Register Definitions in Table 10-6. A common JTAG controller is used for all ports.
9.6
Per-Port Resources
Each port has an associated Framer, LIU, BERT, Jitter Attenuator, and Transmit/Receive HDLC controller. Each of the per-port functions has its own register space.
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DS26528 Octal T1/E1/J1 Transceiver
9.7
Device Interrupts
Figure 9-3 diagrams the flow of interrupt conditions from their source status bits through the multiple levels of information registers and mask bits to the interrupt pin. When an interrupt occurs, the host can read the Global Interrupt Information registers GFISR, GLISR, and GBISR to quickly identify which of the eight transceivers is(are) causing the interrupt(s). The host can then read the specific transceiver's Interrupt Information registers (TIIR, RIIR) and the Latched Status Registers (LLSR, BLSR) to further identify the source of the interrupt(s). If TIIR or RIIR is the source, the host will then read Transmit Latched Status or the Receive Latched Status Registers for the source of the interrupt. All Interrupt Information Register bits are real-time bits that will clear once the appropriate interrupt has been serviced and cleared, as long as no additional, un-masked interrupt condition is present in the associated status register. All Latched Status bits must be cleared by the host writing a "1" to the bit location of the interrupt condition that has been serviced. Latched Status bits that have been masked via Interrupt Mask registers will be masked from the Interrupt Information Registers. The Interrupt Mask register bits prevent individual Latched Status conditions from generating an interrupt, but they do not prevent the Latched Status bits from being set. Therefore, when servicing interrupts, the user should XOR the Latched Status with the associated Interrupt Mask in order to exclude bits for which the user wished to prevent interrupt service. This architecture allows the application host to periodically poll the latched status bits for non-interrupt conditions, while using only one set of registers.
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DS26528 Octal T1/E1/J1 Transceiver
Figure 9-3. Device Interrupt Information Flow Diagram
Receive Remote Alarm Indication Clear Receive Alarm Condition Clear Receive Loss of Signal Clear Receive Loss of Frame Clear Receive Remote Alarm Indication Receive Alarm Condition Receive Loss of Signal Receive Loss of Frame Receive Signal All Ones Receive Signal All Zeros Receive CRC4 Multiframe Receive Align Frame Loss of Receive Clk Clear / Loss of Receive Clk Clear Spare Code Detected Condition Clear / Loop Down Code Clear / V52 Link Clear Loop Up Code Clear / Receive Distant MF Alarm Clear Loss of Receive Clk / Loss of Receive Clk Spare Code Detect / Loop Down Detect / V52 Link Detect Loop Up Detect / Receive Distant MF Alarm Detect Receive Elastic Store Full Receive Elastic Store Empty Receive Elastic Store Slip Receive Signaling Change of State (Enable in RSCSE1-4) One Second Timer Timer Receive Multiframe Receive FIFO Overrun Receive HDLC Opening Byte Receive Packet End Receive Packet Start Receive Packet High Watermark Receive FIFO Not Empty Receive RAI-CI Receive AIS-CI Receive SLC-96 Alignment Receive FDL Register Full Receive BOC Clear Receive BOC Transmit Elastic Store Full Transmit Elastic Store Empty Transmit Elastic Store Slip Transmit SLC96 Multiframe Transmit Pulse Density Violation / Transmit Align Frame Transmit Multiframe Loss of Transmit Clock Clear Loss of Transmit Clock Transmit FDL Register Empty Transmit FIFO Underrun Transmit Message End Transmit FIFO Below Low Watermark Transmit FIFO Not Full Set Loss of Frame Loss of Frame Synchronization Jitter Attenuator Limit Trip Clear Open Circuit Detect Clear Short Circuit Detect Clear Loss of Signal Detect Clear Jitter Attenuator Limit Trip Open Circuit Detect Short Circuit Detect Loss of Signal Detect BERT Bit Error Detected BERT Bit Counter Overflow BERT Error Counter Overflow BERT Receive All Ones BERT Receive All Zeros BERT Receive Loss of Synchronization BERT in Synchronization 7 6 5 4 3 2 1 0 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 3 2 1 0 5 4 3 2 1 0 5 4 3 2 1 0 7 6 5 4 3 2 1 0 4 3 2 1 0 1 0 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0
Drawing Legend:
RLS1 RIM1 0
Interrupt Status Registers Interrupt Mask Registers
Register Name
RIM2
RLS 2
1
Register Name
RLS3
RIM3
2
RLS4
RIM4
3
RLS5
RIM5
4 RLS7 RIM7
RIIR
Framers 2-8
5 TLS1
2 TLS2 TIM2
1
LSIMR
LLSR
0
BLSR
BSIM
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
GFISR1
GFIMR
TIM1
BERTs 2-8
GBISR1
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GBIMR
Interrupt Pin
TIIR
LIUs 2-8
GTCR1.0
GLISR1
TLS3
TIM3
GLIMR
DS26528 Octal T1/E1/J1 Transceiver
9.8
System Backplane Interface
The DS26528 provides a versatile Backplane interface that can be configured to: * Transmit and Receive 2 Frame Elastic Stores * Mapping of T1 channels into a 2.048MHz backplane * IBO mode for multiple framers to share the backplane signals * Transmit and receive channel blocking capability * Fractional T1/E1/J1 support * Hardware-based (through the backplane interface) or processor-based signaling * Flexible backplane clock providing frequencies of 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz * Backplane clock and frame pulse (TSSYNIO) generator
9.8.1
Elastic Stores
The DS26528 contains dual, two-frame elastic stores for each framer; one for the receive direction, and one for the transmit direction. Both elastic stores are fully independent. The transmit and receive side elastic stores can be enabled/disabled independently of each other. Also, the transmit or receive elastic store can interface to either a 1.544MHz or 2.048/4.096/8.192/16.384MHz backplane without regard to the backplane rate for the other elastic store. Since the DS26528 has a common TSYSCLK and RSYSCLK for all eight ports, the backplane signals in each direction must be synchronous for all ports on which the elastic stores are enabled. However, the transmit and receive signals are not required to be synchronous to each other. The TIOCR and RIOCR settings should be identical for all ports on which the elastic stores are enabled. The elastic stores have two main purposes. First, they can be used for rate conversion. When the DS26528 is in the T1 mode, the elastic stores can rate convert the T1 data stream to a 2.048MHz backplane. In E1 mode the elastic store can rate convert the E1 data stream to a 1.544MHz backplane. Secondly, they can be used to absorb the differences in frequency and phase between the T1 or E1 data stream and an asynchronous (i.e., not locked) backplane clock (which can be 1.544MHz or 2.048MHz). In this mode, the elastic stores will manage the rate difference and perform controlled slips, deleting or repeating frames of data in order to manage the difference between the network and the backplane. If the elastic store is enabled while in E1 mode, then either CAS or CRC4 multiframe boundaries will be indicated via the RMSYNC output as controlled by the RSMS2 control bit (RIOCR.1). If the user selects to apply a 1.544MHz clock to the RSYSCLK pin, then the RBCS registers will determine which channels of the received E1 data stream will be deleted. In this mode an F-bit location is inserted into the RSER data and set to one. Also, in 1.544MHz applications, the RCHBLK output will not be active in Channels 25 through 32 (or in other words, RCBR4 is not active). If the two-frame elastic buffer either fills or empties, a controlled slip will occur. If the buffer empties, then a full frame of data will be repeated at RSER and the RLS4.5 and RLS4.6 bits will be set to a one. If the buffer fills, then a full frame of data will be deleted and the RLS4.5 and RLS4.7 bits will be set to a one. The elastic stores can also be used to multiplex T1 or E1 data streams into higher backplane rates. This is the Interleave Bus Option (IBO), which is discussed in Section 9.8.2. The registers related to the Elastic Stores are shown in the following table.
Table 9-2. Registers Related to the Elastic Store
REGISTER Receive I/O Configuration Register (RIOCR) Receive Elastic Store Control Register (RESCR) Receive Latched Status Register 4 ( RLS4) Receive Interrupt Mask Register 4(RIM4) Transmit Elastic Store Control Register (TESCR) Transmit Latched Status Register 1 (TLS1) Transmit Interrupt Mask Register 1 ( TIM1) FRAMER 1 ADDRESSES 084 085 093 0A3 185 190 1A0 FUNCTION Sync and Clock Selection for the Receiver Receive Elastic Store Control Receive Elastic Store Empty full status Receive Interrupt Mask for Elastic Store Transmit elastic control such as minimum mode Transmit Elastic Store Latched Status Transmit Elastic Store Interrupt Mask
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer N = (Framer 1 address + (n - 1) x 200hex), where n = 2 to 8 for Framers 2 to 8.
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DS26528 Octal T1/E1/J1 Transceiver
9.8.1.1 Elastic Stores Initialization
There are two elastic store initializations that may be used to improve performance in certain applications, Elastic Store Reset and Elastic Store Align. Both of these involve the manipulation of the elastic store's read and write pointers and are useful primarily in synchronous applications (RSYSCLK/TSYSCLK are locked to RCLK/TCLK respectively). The elastic store reset is used to minimize the delay through the elastic store. The elastic store align bit is used to 'center' the read/write pointers to the extent possible.
Table 9-3. Elastic Store Delay After Initialization
INITIALIZATION Receive Elastic Store Reset Transmit Elastic Store Reset Receive Elastic Store Align Transmit Elastic Store Align
N = 9 for RSZS = 0 N = 2 for RSZS = 1
REGISTER BIT RESCR.2 TESCR.2 RESCR.3 TESCR.3
DELAY N bytes < Delay < 1 Frame + N bytes N bytes < Delay < 1 Frame + N bytes 1/2 Frame < Delay < 1 1/2 Frames 1/2 Frame < Delay < 1 1/2 Frames
9.8.1.2 Minimum Delay Mode
Elastic store minimum delay mode may be used when the elastic store's system clock is locked to its network clock (i.e., RCLK locked to RSYSCLK for the receive side and TCLK locked to TSYSCLK for the transmit side). RESCR.1 enable the receive elastic store minimum delay mode. When enabled the elastic stores will be forced to a maximum depth of 32 bits instead of the normal two-frame depth. This feature is useful primarily in applications that interface to a 2.048MHz bus. Certain restrictions apply when minimum delay mode is used. In addition to the restriction mentioned above, RSYNC must be configured as an output when the receive elastic store is in minimum delay mode and TSYNC must be configured as an output when transmit minimum delay mode is enabled. In this mode the SYNC outputs are always in frame mode (multiframe outputs are not allowed). In a typical application RSYSCLK and TSYSCLK are locked to RCLK, and RSYNC (frame output mode) is connected to TSSYNCIO (frame input mode). The slip zone select bit (RSZS at RESCR.4) must be set to `1'. All of the slip contention logic in the framer is disabled (since slips cannot occur). On power-up after the RSYSCLK and TSYSCLK signals have locked to their respective network clock signals, the elastic store reset bit (RESCR.2) should be toggled from a zero to a one to insure proper operation
9.8.1.3 Additional Receive Elastic Store Information
If the receive side elastic store is enabled, then the user must provide either a 1.544MHz or 2.048MHz clock at the RSYSCLK pin. For higher rate system clock applications, see Section 9.8.2. The user has the option of either providing a frame/multiframe sync at the RSYNC pin or having the RSYNC pin provide a pulse on frame/multiframe boundaries. If Signaling Reinsertion is enabled, the robbed-bit signaling data is realigned to the multiframe sync input on RSYNC. Otherwise, a multiframe sync input on RSYNC is treated as a simple frame boundary by the elastic store. The framer will always indicate frame boundaries on the network side of the elastic store via the RFSYNC output whether the elastic store is enabled or not. Multiframe boundaries will always be indicated via the RMSYNC output. If the elastic store is enabled, then RMSYNC will output the multiframe boundary on the backplane side of the elastic store. When the device is receiving T1 and the backplane is enabled for 2.048MHz operation, the RMSYNC signal will output the T1 multiframe boundaries as delayed through the elastic store. When the device is receiving E1 and the backplane is enabled for 1.544MHz operation, the RMSYNC signal will output the E1 multiframe boundaries as delayed through the elastic store. If the user selects to apply a 2.048MHz clock to the RSYSCLK pin, then they can use the backplane blank channel select registers (RBCS1-4) to determine which channels will have the data output at RSER forced to all ones.
9.8.1.4 Receiving Mapped T1 Channels from a 2.048MHz Backplane
Setting the TSCLKM bit in TIOCR.4 will enable the transmit elastic store to operate with a 2.048MHz backplane (32 time slots / frame). In this mode the user can chose which of the backplane channels on TSER will be mapped into the T1 data stream by programming the Transmit Blank Channel Select registers (TBCS1-4). A logic '1' in the associated bit location will force the transmit elastic store to ignore backplane data for that channel. Typically the
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DS26528 Octal T1/E1/J1 Transceiver user will want to program eight channels to be ignored. The default (power-up) configuration will ignore channels 25 to 32, so that the first 24 backplane channels are mapped into the T1 transmit data stream. For example, if the user desired to transmit data from the 2.048MHz backplane channels 2-16 and 18-26, the TBCS registers should be programmed as follows: TBCS1 = 01h :: ignore backplane channel 1 :: TBCS2 = 00h TBCS3 = 01h :: ignore backplane channel 17 :: TBCS4 = FCh :: ignore backplane channels 27-32 ::
9.8.1.5
Mapping T1 Channels Onto a 2.048MHz Backplane
Setting the RSCLKM bit in RIOCR.4 will enable the receive elastic store to operate with a 2.048MHz backplane (32 time slots/frame). In this mode the user can chose which of the backplane channels on RSER receive the T1 data by programming the Receive Blank Channel Select registers (RBCS1-4). A logic '1' in the associated bit location will force RSER high for that backplane channel. Typically the user will want to program eight channels to be 'blanked.' The default (power-up) configuration will blank channels 25 to 32, so that the 24 T1 channels are mapped into the first 24 channels of the 2.048MHz backplane. If the user chooses to blank channel 1 (TS0) by setting RBCS1.0 = 1, then the F-bit will be passed into the MSB of TS0 on RSER. For example, if: RBCS1 = 01h RBCS2 = 00h RBCS3 = 01h RBCS4 = FCh Then on RSER: channel 1 (MSB) = F-bit channel 1 (bits 1-7) = all ones channels 2-16 = T1 channels 1-15 channel 17 = all ones channels 18-26 = T1 channels 16-24 channels 27-32 = all ones Note that when two or more sequential channels are chosen to be blanked, the receive slip zone select bit should be set to zero. If the blank channels are distributed (such as 1, 5, 9, 13, 17, 21, 25, 29) then the RSZS bit can be set to one, which may provide a lower occurrence of slips in certain applications. If the two-frame elastic buffer either fills or empties, a controlled slip will occur. If the buffer empties, then a full frame of data will be repeated at RSER and the RLS4.5 and RLS4.6 bits will be set to a one. If the buffer fills, then a full frame of data will be deleted and the RLS4.5 and RLS4.7 bits will be set to a one
9.8.1.6 Receiving Mapped E1 Transmit Channels from a 1.544MHz Backplane
The user can use the TSCLKM bit in TIOCR.4 to enable the transmit elastic store to operate with a 1.544MHz backplane (24 channels / frame + F-bit). In this mode the user can chose which of the E1 time slots will have all ones data inserted by programming the Transmit Blank Channel Select registers (E1TBCS1-4). A logic '1' in the associated bit location will cause the elastic store to force all ones at the outgoing E1 data for that channel. Typically the user will want to program eight channels to be 'blanked'. The default (power-up) configuration will blank channels 25 to 32, so that the first 24 E1 channels are mapped from the 24 channels of the 1.544MHz backplane.
9.8.1.7 Mapping E1 Channels onto a 1.544MHz Backplane
The user can use the RSCLKM bit in RIOCR.4 to enable the receive elastic store to operate with a 1.544MHz backplane (24 channels / frame + F-bit). In this mode the user can chose which of the E1 time slots will be ignored (not transmitted onto RSER) by programming the Receive Blank Channel Select registers (RBCS1-4). A logic '1' in the associated bit location will cause the elastic store to ignore the incoming E1 data for that channel. Typically, the user will want to program eight channels to be 'ignored'. The default (power-up) configuration will ignore channels
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DS26528 Octal T1/E1/J1 Transceiver 25 to 32, so that the first 24 E1 channels are mapped into the 24 channels of the 1.544MHz backplane. In this mode the F-bit location at RSER is always set to 1. For example, if the user wants to ignore E1 time slots 0 (channel 1) and TS 16 (channel 17), the RBCS registers would be programmed as follows: RBCS1 = 01h RBCS2 = 00h RBCS3 = 01h RBCS4 = FCh
9.8.2
IBO Multiplexer
The IBO (Interleaved Bus Operation) multiplexer is used in conjunction with the IBO function located within each framer/formatter block (controlled by the RIBOC and TIBOC registers). When enabled, the IBO multiplexer simplifies user interface by connecting bus signals internally. The IBO multiplexer eliminates the need for ganged external wiring and tri-state output drivers on the RSER and RSIG pins. This option provides a more controlled, cleaner, and lower power mode of operation. Note that the channel block signals TCHBLK and RCHBLK are output at the rate of the of IBO selection. Hence a 4.096MHz IBO would have the channel blocks (if programmed active at the rate of 4.096MHz). Hence the particular blocking channel would be active for a duration of the channel if programmed. The DS26528 will also support the traditional mode of IBO operation by allowing complete access to individual framers, and tri-stating the RSER and RSIG pins at the appropriate times for external bus wiring. This mode of operation is enabled per framer in the associated RIBOC and TIBOC registers, while leaving the IBO multiplexer is disabled (IBOMS0 = 0 and IBOMS1 = 0). Figures show the equivalent internal circuit for each IBO mode. Table 9-4 describes the pin function changes for each mode of the IBO multiplexer.
Table 9-4. Registers related to the IBO Multiplexer
REGISTER Global Transceiver Control Register 1 (GTCR1) Receive Interleave Bus Operation Control Register (RIBOC) Transmit Interleave Bus Operation Control Register (TIBOC) FRAMER 1 ADDRESSES 00F0 88H FUNCTION This is a Global Register for all 8 Framers. It can be used to specify Ganged Operation for the IBO This register can be used for control of how many Framers and the corresponding Speed for the IBO links for the Receiver. This register can be used for control of how many Framers and the corresponding Speed for the IBO links for the Transmitter.
188H
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer N = (Framer 1 address + (n - 1) x 200hex), where n = 2 to 8 for Framers 2 to 8.
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DS26528 Octal T1/E1/J1 Transceiver
Figure 9-5. IBO Multiplexer Equivalent Circuit--4.096MHz
RSER1
RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK
RSIG1 RSYNC1 RSYSCLK TSER1 TSIG1 TSSYNCIO TSYSCLK
Port # 1 Backplane Interface
Port # 2 Backplane Interface
RSER3 RSIG3 RSYNC3 RSYSCLK TSER3 TSIG3 TSSYNCIO TSYSCLK
Port # 3 Backplane Interface
Port # 4 Backplane Interface
RSER5 RSIG5 RSYNC5 RSYSCLK TSER5 TSIG5 TSSYNCIO TSYSCLK
Port # 5 Backplane Interface
Port # 6 Backplane Interface
RSER7 RSIG7 RSYNC7 RSYSCLK TSER7 TSIG7 TSSYNCIO TSYSCLK
Port # 7 Backplane Interface
Port # 8 Backplane Interface
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Figure 9-7. IBO Multiplexer Equivalent Circuit--8.192MHz
RSER1
RSIG1
RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSSYNC TSYSCLK TSER TSIG
Port # 1 Backplane Interface
RSYNC1 RSYSCLK TSER1 TSIG1 TSSYNCIO TSYSCLK
Port # 2 Backplane Interface
Port # 3 Backplane Interface
Port # 4 Backplane Interface
RSER5
RSIG5
RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK
Port # 5 Backplane Interface
RSYNC5 RSYSCLK TSER5 TSIG5 TSSYNCIO TSYSCLK
Port # 6 Backplane Interface
Port # 7 Backplane Interface
Port # 8 Backplane Interface
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Figure 9-9. IBO Multiplexer Equivalent Circuit--16.384MHz
RSER(1) RSER(2) RSER(3) RSER(4) RSER(5) RSER(6) RSER(7) RSER(8) RIBO_OEB(1-8)
RSER1
RSIG(1) RSIG(2) RSIG(3) RSIG(4) RSIG(5) RSIG(6) RSIG(7) RSIG(8) RIBO_OEB(1-8)
RSIG1
Port # 1 Backplane Interface
RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK RSER RSIG RIBO_OEB RSYNC RSYSCLK TSER TSIG TSSYNC TSYSCLK
To Mux
RSYNC1 RSYSCLK TSER1 TSIG1 TSSYNCIO TSYSCLK
To Mux
Port # 2 Backplane Interface
To Mux
Port # 3 Backplane Interface
To Mux
Port # 4 Backplane Interface
To Mux
Port # 5 Backplane Interface
To Mux
Port # 6 Backplane Interface
To Mux
Port # 7 Backplane Interface
To Mux
Port # 8 Backplane Interface
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Table 9-5. RSER Output Pin Definitions
PIN NAME
RSER1 RSER2 RSER3 RSER4 RSER5 RSER6 RSER7 RSER8
NORMAL USE
Rx Serial Data for Port # 1 Rx Serial Data for Port # 2 Rx Serial Data for Port # 3 Rx Serial Data for Port # 4 Rx Serial Data for Port # 5 Rx Serial Data for Port # 6 Rx Serial Data for Port # 7 Rx Serial Data for Port # 8
4.096MHz IBO
Combined Rx Serial Data for Ports 1 & 2 Reserved Combined Rx Serial Data for Ports 3 & 4 Unused Combined Rx Serial Data for Ports 5 & 6 Unused Combined Rx Serial Data for Ports 7 & 8 Unused
8.192MHz IBO
Combined Rx Serial Data for Ports 1, 2, 3, & 4 Unused Unused Unused Combined Rx Serial Data for Ports 5, 6, 7, & 8 Unused Unused Unused
16.384MHz IBO
Rx Serial Data for Ports 1, 2, 3, 4, 5, 6, 7, & 8 Unused Unused Unused Unused Unused Unused Unused
Table 9-6. RSIG Output Pin Definitions
PIN NAME
RSIG1 RSIG2 RSIG3 RSIG4 RSIG5 RSIG6 RSIG7 RSIG8
NORMAL USE
Rx Signaling Data for Port # 1 Rx Signaling Data for Port # 2 Rx Signaling Data for Port # 3 Rx Signaling Data for Port # 4 Rx Signaling Data for Port # 5 Rx Signaling Data for Port # 6 Rx Signaling Data for Port # 7 Rx Signaling Data for Port # 8
4.096MHz IBO
Combined Rx Signaling Data for Ports 1 & 2 Unused Combined Rx Signaling Data for Ports 3 & 4 Unused Combined Rx Signaling Data for Ports 5 & 6 Unused Combined Rx Signaling Data for Ports 7 & 8 Unused
8.192MHz IBO
Combined Rx Signaling Data for Ports 1, 2, 3, & 4 Unused Unused Unused Combined Rx Signaling Data for Ports 5, 6, 7, & 8 Unused Unused Unused
16.384MHz IBO
Rx Signaling Data for Ports 1, 2, 3, 4, 5, 6, 7, & 8 Unused Unused Unused Unused Unused Unused Unused
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Table 9-7. TSER Input Pin Definitions
PIN NAME
TSER1 TSER2 TSER3 TSER4 TSER5 TSER6 TSER7 TSER8
NORMAL USE
Tx Serial Data for Port # 1 Tx Serial Data for Port # 2 Tx Serial Data for Port # 3 Tx Serial Data for Port # 4 Tx Serial Data for Port # 5 Tx Serial Data for Port # 6 Tx Serial Data for Port # 7 Tx Serial Data for Port # 8
4.096MHz IBO
Combined Tx Serial Data for Ports 1 & 2 Unused Combined Tx Serial Data for Ports 3 & 4 Unused Combined Tx Serial Data for Ports 5 & 6 Unused Combined Tx Serial Data for Ports 7 & 8 Unused
8.192MHz IBO
Combined Tx Serial Data for Ports 1, 2, 3, & 4 Unused Unused Unused Combined Tx Serial Data for Ports 5, 6, 7, & 8 Unused Unused Unused
16.384MHz IBO
Tx Serial Data for Ports 1, 2, 3, 4, 5, 6, 7, & 8 Unused Unused Unused Unused Unused Unused Unused
Table 9-8. TSIG Input Pin Definitions
PIN NAME
TSIG1 TSIG2 TSIG3 TSIG4 TSIG5 TSIG6 TSIG7 TSIG8
NORMAL USE
Tx Signaling Data for Port # 1 Tx Signaling Data for Port # 2 Tx Signaling Data for Port # 3 Tx Signaling Data for Port # 4 Tx Signaling Data for Port # 5 Tx Signaling Data for Port # 6 Tx Signaling Data for Port # 7 Tx Signaling Data for Port # 8
4.096MHz IBO
Combined Tx Signaling Data for Ports 1 & 2 Unused Combined Tx Signaling Data for Ports 3 & 4 Unused Combined Tx Signaling Data for Ports 5 & 6 Unused Combined Tx Signaling Data for Ports 7 & 8 Unused
8.192MHz IBO
Combined Tx Signaling Data for Ports 1, 2, 3, & 4 Unused Unused Unused Combined Tx Signaling Data for Ports 5, 6, 7, & 8 Unused Unused Unused
16.384MHz IBO
Tx Signaling Data for Ports 1, 2, 3, 4, 5, 6, 7, & 8 Unused Unused Unused Unused Unused Unused Unused
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Table 9-9. RSYNC Input Pin Definitions
PIN NAME
RSYNC1 RSYNC2 RSYNC3 RSYNC4 RSYNC5 RSYNC6 RSYNC7 RSYNC8
NORMAL USE
Rx Frame Pulse for port # 1 Rx Frame Pulse for port # 2 Rx Frame Pulse for port # 3 Rx Frame Pulse for port # 4 Rx Frame Pulse for port # 5 Rx Frame Pulse for port # 6 Rx Frame Pulse for port # 7 Rx Frame Pulse for port # 8
4.096MHz IBO
Rx Frame Pulse for Ports 1 & 2 Unused Rx Frame Pulse for Ports 3 & 4 Unused Rx Frame Pulse for Ports 5 & 6 Unused Rx Frame Pulse for Ports 7 & 8 Unused
8.192MHz IBO
Rx Frame Pulse for Ports 1, 2, 3, & 4 Unused Unused Unused Rx Frame Pulse for Ports 5, 6, 7, & 8 Unused Unused Unused
16.384MHz IBO
Rx Frame Pulse for Ports 1, 2, 3, 4, 5, 6, 7, & 8 Unused Unused Unused Unused Unused Unused Unused
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9.8.3
H.100 (CT-Bus) Compatibility
The registers used for controlling the H.100 Backplane are RIOCR and TIOCR. The H.100 (or CT Bus) is a synchronous, bit-serial, TDM transport bus operating at 8.192MHz. The H.100 standard also allows compatibility modes to operate at 2.048MHz, 4.096MHz, or 8.192MHz. The control bit H100EN (RIOCR.5), when combined with RSYNCINV and TSSYNCINV allows the DS26528 to accept a CT-Bus-compatible frame sync signal (/CT_FRAME) at the RSYNC and TSSYNCIO (input mode) inputs. The following rules apply to the H100EN control bit: 1. The H100EN bit controls the sampling point for the RSYNC (input mode) and TSSYNCIO (input Mode) only (the RSYNC output and other sync signals are not affected). 2. The H100EN bit would always be used in conjunction with the receive and transmit elastic store buffers. 3. The H100EN bit would typically be used with 8.192MHz IBO mode, but could also be used with 4.096MHz IBO mode or 2.048MHz backplane operation. 4. The H100EN bit in RIOCR controls both RSYNC and TSSYNCIO (i.e., there is no separate control bit for the TSSYNCIO). 5. The H100EN bit does NOT invert the expected signal; RSYNCINV (RIOCR) and TSSYNCINV (TIOCR) must be set `high' to invert the inbound sync signals.
Figure 9-11. RSYNC Input In H.100 (Ct-Bus) Mode
RSYNC1
RSYNC2 RSYSCLK
RSER
Bit 8
Bit 1
Bit 2
tbc3
NOTES: 1) RSYNC input mode, in normal operation. 2) RSYNC input mode, H100EN = 1 and RSYNCINV = 1. 3) tbc (bit-cell time) = 122ns typically. tbc = 244ns or 488ns also acceptable.
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Figure 9-13. TSSYNCIO (Input Mode) Input In H.100 (CT-Bus) Mode
TSSYNCIO1
TSSYNCIO2 TSYSCLK
TSER
Bit 8
Bit 1
Bit 2
tbc3
NOTES: 1) TSSYNCIO in normal operation 2) TSSYNCIO with H100EN = 1 and TSSYNCINV = 1. 3) tbc (bit-cell time) = 122ns typically. tbc = 244ns or 488ns also acceptable.
9.8.4
Transmit and Receive Channel Blocking Registers
The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3/RCBR4) and the Transmit Channel Blocking Registers (TCBR1/TCBR2/TCBR3/TCBR4) control RCHBLK and TCHBLK pins respectively. The RCHBLK and TCHBLK pins are user programmable outputs that can be forced either high or low during individual channels. These outputs can be used to block clocks to a USART or LAPD controller in ISDN-PRI applications. When the appropriate bits are set to a one, the RCHBLK and TCHBLK pin will be held high during the entire corresponding channel time. When used with a T1 (1.544MHz) backplane, only TCBR1 to TCBR3 will be used. TCBR4 is included to support an E1 (2.048MHz) backplane when the elastic store is configured for T1 to E1 rate conversion (Elastic Store).
9.8.5
Transmit Fractional Support (Gapped Clock Mode)
The DS26528 can be programmed to output gapped clocks for selected channels in the receive and transmit paths to simplify connections into a USART or LAPD controller in Fractional T1/E1 or ISDN-PRI applications. When the gapped clock feature is enabled, a gated clock is output on the TCHCLK signal. The channel selection is controlled via the transmit gapped clock channel select registers (TGCCS1-TGCCS4). The transmit path is enabled for gapped clock mode with the TGCLKEN bit (TESCR.6). Both 56KBps and 64KBps channel formats are supported as determined by TESCR.7. When 56KBps mode is selected, the clock corresponding to the Data/Control bit in the channel is omitted (only the seven most significant bits of the channel have clocks).
9.8.6
Receive Fractional Support (Gapped Clock Mode)
The DS26528 can be programmed to output gapped clocks for selected channels in the receive and transmit paths to simplify connections into a USART or LAPD controller in Fractional T1/E1 or ISDN-PRI applications. When the gapped clock feature is enabled, a gated clock is output on the RCHCLK signal. The channel selection is controlled via the receive gapped clock channel select registers (RGCCS1-RGCCS4). The receive path is enabled for gapped clock mode with the RGCLKEN bit (RESCR.6). Both 56KBps and 64KBps channel formats are supported as determined by RESCR.7. When 56KBps mode is selected, the clock corresponding to the Data/Control bit in the channel is omitted (only the seven most significant bits of the channel have clocks).
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9.9
Framers
The DS26528 framer cores are software selectable for T1, J1, or E1. The receive framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It is also used for extracting and inserting signaling data, T1 FDL data, and E1 Si, and Sa bit information. The receive side framer decodes AMI, B8ZS line coding, synchronizes to the data stream, reports alarm information, counts framing/coding and CRC errors, and provides clock/data and frame sync signals to the backplane interface section. Diagnostic capabilities include loopbacks, and 16-bit loop-up and loop-down code detection. The device contains a set of internal registers for host access and control of the device. On the transmit side, clock data and frame sync signals are provided to the framer by the backplane interface section. The framer inserts the appropriate synchronization framing patterns, alarm information, calculates and inserts the CRC codes, and provides the B8ZS (zero code suppression) and AMI line coding. Both the transmit and receive path have an HDLC controller. The HDLC controller transmits and receives data via the framer block. The HDLC controller may be assigned to any time slot, portion of a time slot, or to FDL (T1). The HDLC controller has separate 64-byte Tx and Rx FIFO to reduce the amount of processor overhead required to manage the flow of data. The backplane interface provides a versatile method of sending and receiving data from the host system. Elastic stores provide a method for interfacing to asynchronous systems, converting from a T1/E1 network to a 2.048MHz, 4.096MHz, 8.192MHz or N x 64kHz system backplane. The elastic stores also manage slip conditions (asynchronous interface). An IBO (Interleave Bus Option) is provided to allow multiple framers in the DS26528 to share a high-speed backplane.
9.9.1
T1 Framing
DS1 trunks contain 24 bytes of serial voice/data channels bundled with an overhead bit, the F-bit. The F-bit contains a fixed pattern for the receiver to delineate the frame boundaries. The F-bit is inserted once per frame at the beginning of the transmit frame boundary. The frames are further grouped into bundles of frames 12 for D4 and 24 for ESF. The D4 and ESF framing modes are outlined in Table 9-10 and Table 9-11. In the D4 Mode, framing bit for Frame 12 is ignored if Japanese Yellow is selected.
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Table 9-10. D4 Framing Mode
FRAME NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 Ft 1 0 0 0 1 1 0 1 1 1 0 0 B A Fs SIGNALING
Table 9-11. ESF Framing Mode
FRAME NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 FRAMING FDL O 0 O O O O O O 0 O O 1 O O 1 O CRC6 O CRC5 O CRC3 O CRC4 CRC2 O CRC CRC1 SIGNALING
0
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Table 9-12. SLC-96 Framing
FRAME NUMBER
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58
Ft
1
Fs
0
SIGNALING
0 0 1 1 0 1 1 1 0 0 1 0 0 0 1 1 0 1 1 1 0 C1 (concentrator bit) 1 C2 (concentrator bit) 0 C3 (concentrator bit) 1 C4 (concentrator bit) 0 C5 (concentrator bit) 1 C6 (concentrator bit) 0 C7 (concentrator bit) 1 C8 (concentrator bit) 0 C9 (concentrator bit) 1 C10 (concentrator bit) 0 C11 (concentrator bit) 1 0 (spoiler Bit) 0 1 (Spoiler Bit) 1 0 (Spoiler Bit) 0 M1 (Maintenance Bit) 1 M2 (Maintenance Bit) 0 M3 (Maintenance Bit) 1 A1 (Alarm Bit) A D C B A D C B A
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FRAME NUMBER
59 60 61 62 63 64 65 66 67 68 69 70 71 72
Ft
0
Fs
A2 (Alarm Bit)
SIGNALING
B
1 S1 (Switch Bit) 0 S2 (Switch Bit) 1 S3 (Switch Bit) 0 S4 (Switch Bit) 1 1(Spoiler Bit) 0 0 D C
9.9.2
E1 Framing
The E1 Framing consists of FAS, NFAS detection as shown in the following table.
Table 9-13. E1 FAS/NFAS Framing
CRC-4 FRAME # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TYPE FAS NFAS FAS NFAS FAS NFAS FAS NFAS FAS NFAS FAS NFAS FAS NFAS FAS NFAS 1 C1 0 C2 0 C3 1 C4 0 C1 1 C2 1 C3 E1 C4 E2 2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 3 0 A 0 A 0 A 0 A 0 A 0 A 0 A 0 A 4 1 Sa4 1 Sa4 1 Sa4 1 Sa4 1 Sa4 1 Sa4 1 Sa4 1 Sa4 5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 1 Sa5 6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 0 Sa6 7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 1 Sa7 8 1 Sa8 1 Sa8 1 Sa8 1 Sa8 1 Sa8 1 Sa8 1 Sa8 1 Sa8
C -- C bits are the CRC-4 remainder. A -- Alarm bits. Sa -- Bits for Datalink.
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DS26528 Octal T1/E1/J1 Transceiver Registers that are related to setting up the framing are shown in the following table.
Table 9-14. Registers Related to Setting Up the Framer
REGISTER Transmit Master Mode Register (TMMR) Transmit Control Register 1 (TCR1) Transmit Control Register 2 (TCR2) Transmit Control Register 3 (TCR3) Receive Master Mode Register (RMMR) Receive Control Register 1 (RCR1) T1 Receive Control Register 2 (T1RCR2) E1 Receive Control Register 2 (E1RCR2) Receive Latched Status Register 1 (RLS1) Receive Interrupt Mask Register 1 (RIM1) Receive Latched Status Register 2 (RLS2) Receive Interrupt Mask Register 2 (RIM2) Receive Latched Status Register 4 ( RLS4) E1 Receive Interrupt Mask Register 4 (RIM4) Frames Out Of Sync Count Register 1 (FOSCR1) Frames Out Of Sync Count Register 2 (FOSCR2) E1 Receive Align Frame Register (E1RAF) E1 Receive Non-Align Frame Register (E1RNAF) Transmit SLC96 Control Register (T1TSLC1) Transmit SLC96 Control Register (T1TSLC2) Transmit SLC96 Control Register (T1TSLC3) Receive SLC96 Control Register 1 (T1RSLC1) Receive SLC96 Control Register 1(T1RSLC2) Receive SLC96 Control Register 1 (T1RSLC3) FRAMER 1 ADDRESSES 180 181 182 183 080 081 014 082 90 A0 91 A1 93 A3 54 55 64 65 164 165 166 064 065 066 T1E1 Mode Source of the F-Bit F-Bit Corruption, Selection of SLC96 ESF or D4 Mode Selection T1/E1 Selection for Receiver Resynchronization Criteria for the Framer T1 Remote Alarm and OOF Criteria E1 Receive Loss of Signal Criteria Selection Receive Latched Status 1 Receive Interrupt Mask 1 Receive Latched Status 2 Receive Interrupt Mask 2 Receive Latched Status 4 Receive Interrupt Mask 4 Framer Out of Sync Register 1 Framer Out of Sync Register 2 RAF Byte RNAF Byte Transmit SLC96 Bits Transmit SLC96 Bits Transmit SLC96 Bits Receive SLC96 Bits Receive SLC96 Bits Receive SLC96 Bits FUNCTION
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 - 8 can be calculated using the following: Framer N = (Framer 1 address + (n-1) x 200hex); where n = 2 to 8 for Framers 2 to 8.
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9.9.3
T1 Transmit Synchronizer
The DS26528 transmitter has the ability to identify the D4 or ESF frame boundary, as well as the CRC multiframe boundaries within the incoming NRZ data stream at TSER. The TFM (TCR3.2) control bit determines whether the transmit synchronizer searches for the D4 or ESF multiframe. Additional control signals for the transmit synchronizer are located in the TSYNCC Register. The latched status bit TLS3.0 (LOFD) is provided to indicate that a Loss of Frame synchronization has occurred, and a real-time bit (LOF) which is set high when the synchronizer is searching for frame/multiframe alignment. The LOFD bit can be enabled to cause an interrupt condition on INTB. Note that when the transmit synchronizer is used, the TSYNC signal should be set as an output (TSIO = 1) and the recovered frame sync pulse will be output on this signal. The recovered CRC4 multi-frame sync pulse will be output if enabled with TIOCR.0 (TSM = 1). Other key points concerning the E1 transmit synchronizer: 1. The Tx synchronizer is not operational when the transmit elastic store is enabled, including IBO modes. 2. The Tx synchronizer does not perform CRC6 alignment verification (ESF mode) and does not verify CRC4 codewords. The Tx synchronizer does not have the ability to search for the CAS multiframe. The registers related to the Transmit Synchronizer are shown in the following table.
Table 9-15. Registers Related to the Transmit Synchronizer
REGISTER Transmit Synchronizer Control Register (TSYNCC) Transmit Control Register 3 (TCR3) Transmit Latched Status Register 3 (TLS3) Transmit Interrupt Mask Register 3 (TIM3) Transmit I/O Configuration Register (TIOCR) FRAMER 1 ADDRESSES 18E 183 192 1A2 184 FUNCTION Resynchronization Control for the Transmit Synchronizer TFM Bit Selects Between D4 and ESF for the Transmit Synchronizer Provides Latched Status for the Transmit Synchronizer Provides Mask Bits for the TLS3 Status TSYNC Should Be Set as an Output
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 - 8 can be calculated using the following: Framer N = (Framer 1 address + (n-1) x 200hex); where n = 2 to 8 for Framers 2 to 8.
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9.9.4
Signaling
The DS26528 supports both software and hardware based Signaling. Interrupts can be generated on changes of signaling data. The DS26528 is also equipped with receive signaling freeze on loss of synchronization (OOF), carrier loss or change of frame alignment. The DS26528 also has hardware pins to indicate signaling freeze. Flexible signaling support Software or hardware based Interrupt generated on change of signaling data Receive signaling freeze on loss of frame, loss of signal, or change of frame alignment. Hardware pins for carrier loss and signaling freeze indication.
Table 9-16. Registers Related to Signaling
REGISTER Transmit Signaling Registers (TS1 to TS16) Software Signaling Insertion Enable Registers (SSIE1 to SSIE4) Transmit Hardware Signaling Channel Select Registers (THSCS1 to THSCS4) Receive Signaling Control Register (RSIGC) Receive Signaling All-Ones Insertion Registers (T1RSAOI1 to T1RSAOI3) Receive Signaling Registers (RS1 to RS16) RSS1 to RSS4 RSCSE1 to RSCSE4 RLS4 RIM4 RSI1 to RSI4 FRAMER 1 ADDRESSES 140 to 14B (T1/J1) 140 to 14F (E1 CAS) 118, 119, 11A, 11B FUNCTION Transmit ABCD Signaling When Enabled, Signaling is Inserted for the Channel Bits Determine which Channels will have Signaling Inserted in Hardware Signaling Mode Freeze Control for Receive Signaling Registers for All-Ones Insertion (T1 Mode Only) Receive Signaling Bytes Receive Signaling Change of Status Bits Receive Signaling Change of State Interrupt Enable Receive Signaling Change of State Bit Receive Signaling Change of State Interrupt Mask Bit Registers for Signaling Reinsertion
1C8, 1C9, 1CA, 1CB
013 038 to 03A 040 to 04B (T1/J1) 040 to 04F (E1) 098 to 09A (T1/J1) 98 to 9F (E1) A8, A9, AA, AB 93 A3 0C8 to 0CB
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 - 8 can be calculated using the following: Framer N = (Framer 1 address + (n-1) x 200hex); where n = 2 to 8 for Framers 2 to 8.
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9.9.4.1 Transmit Signaling Operation
There are two methods to provide transmit signaling data. These are processor based (i.e., software based) or hardware based. Processor-based refers to access through the transmit signaling registers, TS1 -TS16, while hardware based refers to using the TSIG pins. Both methods may be used simultaneously.
9.9.4.1.1 Processor-Based Signaling
In processor-based mode, signaling data is loaded into the Transmit Signaling registers (TS1 -TS16) via the host interface. On multiframe boundaries, the contents of these registers are loaded into a shift register for placement in the appropriate bit position in the outgoing data stream. The user can utilize the Transmit Multiframe Interrupt in Latched Status Register 1 (TLS1.2) to know when to update the signaling bits. The user need not update any transmit signaling register for which there is no change of state for that register. Each Transmit Signaling Register contains the Robbed Bit signaling (TCR1.4 in T1 mode) or TS16 CAS signaling (TCR1.6 in E1 mode) for one time slot that will be inserted into the outgoing stream. Signaling data can be sourced from the TS registers on a per-channel basis by utilizing the Software Signaling Insertion Enable registers, SSIE1 through SSIE4. In T1 ESF framing mode, there are four signaling bits per channel (A, B, C, and D). TS1 - TS12 contain a full multiframe of signaling data. In T1 D4 framing mode, there are only two signaling bits per channel (A and B). In T1 D4 framing mode, the framer uses A and B bit positions for the next multiframe. The C and D bit positions become `don't care' in D4 mode. In E1 mode, TS16 carries the signaling information. This information can be in either CCS (Common Channel Signaling) or CAS (Channel Associated Signaling) format. The 32 time slots are referenced by two different channel number schemes in E1. In "Channel" numbering, TS0 through TS31 are labeled channels 1 through 32. In "Phone Channel" numbering TS1 through TS15 are labeled channel 1 through channel 15 and TS17 through TS31 are labeled channel 15 through channel 30.
TIME SLOT NUMBERING SCHEMES
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TS Channel 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Phone Channel
9.9.4.1.2
Hardware-Based Signaling
In Hardware Based mode, signaling data is input via the TSIG pin. This signaling PCM stream is buffered and inserted to the data stream being input at the TSER pin. Signaling data may be input via the Transmit Hardware Signaling Channel Select (THSCS1) function, the framer can be set up to take the signaling data presented at the TSIG pin and insert the signaling data into the PCM data stream that is being input at the TSER pin. The user can control which channels are to have signaling data from the TSIG pin inserted into them on a per-channel basis. The signaling insertion capabilities of the framer are available whether the transmit side elastic store is enabled or disabled. If the elastic store is enabled, the backplane clock (TSYSCLK) can be either 1.544MHz or 2.048MHz.
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9.9.4.2 Receive Signaling Operation
There are two methods to access receive signaling data and provide transmit signaling data. These are processor based (i.e., software based) or hardware based. Processor-based refers to access through the transmit and receive signaling registers, RS1-RS16. Hardware based refers to the RSIG pin. Both methods may be used simultaneously.
9.9.4.2.1 Processor-Based Signaling
Signaling information is sampled from the receive data stream and copied into the receive signaling registers, RS1 through RS16. The signaling information in these registers is always updated on multiframe boundaries. This function is always enabled.
9.9.4.2.2 Change Of State
In order to avoid constantly monitoring of the receive signaling registers the DS26528 can be programmed to alert the host when any specific channel or channels undergo a change of their signaling state. RSCSE1 through RSCSE4 are used to select which channels can cause a change of state indication. The change of state is indicated in Latched Status Register 4 (RLS4.3). If signaling integration is enabled then the new signaling state must be constant for 3 multiframes before a change of state indication is indicated. The user can enable the INT pin to toggle low upon detection of a change in signaling by setting the Interrupt Mask bit RIM4.3. The signaling integration mode is global and cannot be enabled on a channel-by-channel basis. The user can identity which channels have undergone a signaling change of state by reading the Receive Signaling Status (RSS1 through RSS4) registers. The information from these registers will tell the user which RSx register to read for the new signaling data. All changes are indicated in the RSS1-RSS4 registers regardless of the RSCSE1-RSCSE4 registers.
9.9.4.2.3 Hardware-Based Receive Signaling
In hardware based signaling the signaling data is can be obtained from the RSER pin or the RSIG pin. RSIG is a signaling PCM stream output on a channel by channel basis from the signaling buffer. The T1 robbed bit or E1 TS16 signaling data is still present in the original data stream at RSER. The signaling buffer provides signaling data to the RSIG pin and also allows signaling data to be reinserted into the original data stream in a different alignment that is determined by a multiframe signal from the RSYNC pin. In this mode, the receive elastic store may be enabled or disabled. If the receive elastic store is enabled, then the backplane clock (RSYSCLK) can be either 1.544MHz or 2.048MHz. In the ESF framing mode, the ABCD signaling bits are output on RSIG in the lower nibble of each channel. The RSIG data is updated once a multiframe (3ms for T1 ESF, 1.5ms for T1 D4, 2ms for E1 CAS) unless a signaling freeze is in effect. In the D4 framing mode, the AB signaling bits are output twice on RSIG in the lower nibble of each channel. Hence, bits 5 and 6 contain the same data as bits 7 and 8, respectively, in each channel.
9.9.4.2.4 Receive Signaling Reinsertion at RSER
In this mode, the user will provide a multiframe sync at the RSYNC pin and the signaling data will be reinserted based on this alignment. In T1 mode, this results in two copies of the signaling data in the RSER data stream. The original signaling data based on the Fs/ESF frame positions and the realigned data based on the user supplied multiframe sync applied at RSYNC. In voice channels this extra copy of signaling data is of little consequence. Reinsertion can be avoided in data channels since this feature is activated on a per-channel basis. For reinsertion, the elastic store must be enabled and for T1, the backplane clock can be either 1.544MHz or 2.048MHz. E1 signaling information cannot be reinserted into a 1.544MHz backplane. Signaling reinsertion mode is enabled, on a per-channel basis by setting the Receive Signaling Reinsertion Channel Select bit high in the RSI register. The channels that are to have signaling reinserted are selected by writing to the RSI1-RSI4 registers. In E1 mode, the user will generally select all channels or none for reinsertion.
9.9.4.2.5 Force Receive Signaling All Ones
In T1 mode, the user can on a per-channel basis force the robbed bit signaling bit positions to a one. This is done by using the T1RSAOI registers (T1RSAOI1 to 3). The user sets the Channel Select bit in the RSAOI1-RSAOI3 registers to select the channels that are to have the signaling forced to one.
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9.9.4.2.6 Receive Signaling Freeze
The signaling data in the four multiframe signaling buffers will be frozen in a known good state upon either a loss of synchronization (OOF event), carrier loss, or change of frame alignment. In T1 mode, this action meets the requirements of BellCore TR-TSY-000170 for signaling freezing. To allow this freeze action to occur, the RSFE control bit (RSIGC.1) should be set high. The user can force a freeze by setting the RSFF control bit (RSIGC.2) high. The RSIGF output pin provides a hardware indication that a freeze is in effect. The four multiframe buffer provides a three multiframe delay in the signaling bits provided at the RSIG pin (and at the RSER pin if Receive Signaling Reinsertion is enabled). When freezing is enabled (RSFE = 1), the signaling data will be held in the last known good state until the corrupting error condition subsides. When the error condition subsides, the signaling data will be held in the old state for at least an additional 9ms (4.5ms in D4 framing mode, 6ms for E1 mode) before being allowed to be updated with new signaling data. The Receive Signaling Registers are frozen and not updated during a loss of sync condition. They will contain the most recent signaling information before the LOF occurred.
9.9.4.3 Transmit SLC-96 Operation (T1 Mode Only)
In a SLC-96 based transmission scheme, the standard Fs bit pattern is robbed to make room for a set of message fields. The SLC-96 multiframe is made up of six D4 superframes, hence it is 72 frames long. In the 72-frame SLC-96 multiframe, 36 of the framing bits are the normal Ft pattern and the other 36 bits are divided into alarm, maintenance, spoiler, and concentrator bits as well as 12-bits of the normal Fs pattern. Additional SLC-96 information can be found in BellCore document TR-TSY-000008. Registers related to the Transmit FDL are shown in the following table.
Table 9-17. Registers Related to SLC96
REGISTER Transmit FDL (T1TFDL) TSCL Registers (T1TSLC1) Transmit Control Register 2 TCR2) Transmit Latched Status 1(TLS1) Receive SLC 96 Register (T1RSLC1) Receive Latched Status 7 (RLS7) FRAMER 1 ADDRESSES 162 164, 165, 166 182 190 64, 64, 66 96 Receive SLC-96 Alignment Event FUNCTION For sending Messages in Transmit SLC-96 Ft/Fs Bits Registers that Control the SLC-96 Overhead Values Transmit Control for Data Selection Source for the Ft/Fs Bits Status Bit for Indicating Transmission of Data Link Buffer
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 - 8 can be calculated using the following: Framer N = (Framer 1 address + (n-1) x 200hex); where n = 2 to 8 for Framers 2 to 8.
The TFDL register is used to insert the SLC-96 message fields. To insert the SLC-96 message using the TFDL register, the user should configure the DS26528 as shown below: * TCR2.6 (TSLC96) = 1 Enable Transmit SLC-96 * TCR2.7 (TFDLS) = 0 Source FS bits via TFDL or SLC96 formatter * TCR3.2 (TFM) = 1 D4 framing Mode * TCR1.6 (TFPT) = 0 Do not 'pass through' TSER F-bits. The DS26528 will automatically insert the 12-bit alignment pattern in the Fs bits for the SLC96 data link frame. Data from the TSLC1-TSLC3 will be inserted into the remaining Fs bit locations of the SLC96 multiframe. The status bit TSLC96 located at TLS1.4 will set to indicate that the SLC-96 data link buffer has been transmitted and that the user should write new message data into TSLC1-TSLC3. The host will have 9ms after the assertion of TLS1.4 to write the registers TSLC1-TSLC3. If no new data is provided in these registers, the previous values will be retransmitted. 51 of 269
DS26528 Octal T1/E1/J1 Transceiver
9.9.4.4 Receive SLC-96 Operation (T1 Mode Only)
In a SLC-96-based transmission scheme, the standard Fs bit pattern is robbed to make room for a set of message fields. The SLC-96 multiframe is made up of six D4 superframes, hence it is 72 frames long. In the 72-frame SLC-96 multiframe, 36 of the framing bits are the normal Ft pattern and the other 36-bits are divided into alarm, maintenance, spoiler, and concentrator bits as well as 12-bits of the normal Fs pattern. Additional SLC-96 information can be found in BellCore document TR-TSY-000008. To enable the DS26528 to synchronize onto a SLC-96 pattern, the following configuration should be used: * RCR1.5 (RFM) = 1 Set to D4 framing mode Set to cross-couple Ft and Fs bits * RCR1.3 (SYNCC) = 1 * T1RCR2.4 (RSLC96) = 1 Enable SLC-96 synchronizer * RCR1.7 (SYNCT) = 0 Set to minimum sync time The SLC-96 message bits can be extracted via the RSLC1-3 registers. The status bit RSLC96 located at RLS7.3 is useful for retrieving SLC-96 message data. The RSLC96 bit will indicate when the framer has updated the data link registers RSLC1-RSLC3 with the latest message data from the incoming data stream. Once the RSLC96 bit is set, the user will have 9ms (or until the next RSLC96 interrupt) to retrieve the most recent message data from the RSLC1/2/3 registers. Note that RSLC96 will not set if the DS26528 is unable to detect the 12-bit SLC-96 alignment pattern.
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DS26528 Octal T1/E1/J1 Transceiver
9.9.5
T1 Datalink
9.9.5.1 T1 Transmit Bit Oriented Code (BOC) Transmit Controller
The DS26528 contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1 mode. The registers related to the Transmit Bit Oriented Code are shown in the following table.
Table 9-18. Registers Related to T1 Transmit BOC
REGISTER Transmit Bit Oriented Register (T1TBOC) Transmit HDLC Control Register 2 (THC2) Transmit Control Register 1(TCR1) FRAMER 1 ADDRESSES 163 113 181 FUNCTION Transmit Bit Oriented Message Code Register Bit to enable Sending of Transmit BOC Determines the Sourcing of the F-Bit
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 - 8 can be calculated using the following: Framer N = (Framer 1 address + (n-1) x 200hex); where n = 2 to 8 for Framers 2 to 8.
Bits 0 through 5 in the TBOC register contain the BOC message to be transmitted. Setting SBOC = 1 (THC2.6) causes the transmit BOC controller to immediately begin inserting the BOC sequence into the FDL bit position. The transmit BOC controller automatically provides the abort sequence. BOC messages will be transmitted as long as SBOC is set. Note that the TFPT(TCR1.6) control bit must be set to 'zero' for the BOC message to overwrite F-bit information being sampled on TSER.
To Transmit a BOC
1. Write 6-bit code into the TBOC register. 2. Set SBOC bit in THC2 = 1.
9.9.5.2 Receive Bit Oriented Code (BOC) Controller
The DS26528 Framers contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1, ESF Mode in the Data link Bits. The following table shows the registers related to the Receive BOC operation.
Table 9-19. Registers Related to T1 Receive BOC
REGISTER Receive Bit Oriented Control (T1RBOCC) Receive Bit Oriented Control (T1RBOC) Receive Latched Status 7(RLS7) Receive Interrupt Mask 7 (RIM7) FRAMER 1 ADDRESSES 015 063 096 0A6 FUNCTION Controls the Receive BOC Function Receive Bit Oriented Message Indicates Changes to the Receive Bit Oriented Messages Mask Bits for RBOC for Generation of Interrupts
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 - 8 can be calculated using the following: Framer N = (Framer 1 address + (n-1) x 200hex); where n = 2 to 8 for Framers 2 to 8.
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DS26528 Octal T1/E1/J1 Transceiver In ESF mode, the DS26528 continuously monitors the receive message bits for a valid BOC message. The BOC Detect (BD) status bit at RLS7.0 will be set once a valid message has been detected for time determined by the Receive BOC Filter bits RBF0 and RBF1 in the RBOCC register. The 6-bit BOC message will be available in the RBOC register. Once the user has cleared the BD bit, it will remain clear until a new BOC is detected (or the same BOC is detected following a BOC Clear event). The BOC Clear (BC) bit at RLS7.1 is set when a valid BOC is no longer being detected for a time determined by the Receive BOC Disintegration bits RBD0 and RBD1 in the RBOCC register. The BD and BC status bits can create a hardware interrupt on the INTB signal as enabled by the associated interrupt mask bits in the RIM7 register.
9.9.5.3 Legacy T1 Transmit FDL
It is recommended that the DS26528's built-in BOC or HDLC controllers be used for most applications requiring access to the FDL. The registers related to control of the Transmit FDL are presented in the following table.
Table 9-20. Registers Related to T1 Transmit FDL
REGISTER Transmit FDL (T1TFDL) Transmit Control 2 (TCR2) Transmit Latched Status 2(TLS2) Transmit Interrupt Mask 2 (TIM2) FRAMER 1 ADDRESSES 162 182 191 1A1 FUNCTION FDL Code Used to Insert Transmit FDL Defines the Source of the FDL Transmit FDL Empty Bit Mask Bit for TFDL Empty
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 - 8 can be calculated using the following: Framer N = (Framer 1 address + (n-1) x 200hex); where n = 2 to 8 for Framers 2 to 8.
When enabled with TCR2.7, the transmit section will shift out into the T1 data stream, either the FDL (in the ESF framing mode) or the Fs bits (in the D4 framing mode) contained in the Transmit FDL register (TFDL). When a new value is written to the TFDL, it will be multiplexed serially (LSB first) into the proper position in the outgoing T1 data stream. After the full eight bits has been shifted out, the framer will signal the host controller that the buffer is empty and that more data is needed by setting the TLS2.4 bit to a one. The INT will also toggle low if enabled via TIM2.4. The user has 2ms to update the TFDL with a new value. If the TFDL is not updated, the old value in the TFDL will be transmitted once again. Note that in this mode, no zero stuffing will be applied to the FDL data. It is strongly suggested that the HDLC controller be used for FDL messaging applications. In the D4 framing mode, the framer uses the TFDL register to insert the Fs framing pattern. To accomplish this the TFDL register must be programmed to `1C'h and TCR2.7 should be set to `0' ( source Fs data from the TFDL register) The Transmit FDL Register (TFDL) contains the Facility Data Link (FDL) information that is to be inserted on a byte basis into the outgoing T1 data stream. The LSB is transmitted first. In D4 mode, only the lower six bits are used.
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DS26528 Octal T1/E1/J1 Transceiver
9.9.5.4 Legacy T1 Receive FDL
It is recommended that the DS26528's built-in BOC or HDLC controllers be used for most applications requiring access to the FDL. The registers related to the Receive FDL are shown in the following table.
Table 9-21. Registers Related to T1 Receive FDL
REGISTER Receive FDL (T1RFDL) Receive Latched Status 7(RLS7) Receive Interrupt Mask 7(RIM7) FRAMER 1 ADDRESSES 162 96 1A1 FUNCTION FDL Code Used to Insert Transmit FDL Receive FDL Full Bit is in this Register Mask Bit for RFDL Full
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 - 8 can be calculated using the following: Framer N = (Framer 1 address + (n-1) x 200hex); where n = 2 to 8 for Framers 2 to 8.
In the receive section, the recovered FDL bits or Fs bits are shifted bit-by-bit into the Receive FDL register (RFDL). Since the RFDL is 8 bits in length, it will fill up every 2ms (8 times 250ms). The framer will signal an external controller that the buffer has filled via the RLS7.2 bit. If enabled via RIM7.2, the INTB pin will toggle low indicating that the buffer has filled and needs to be read. The user has 2ms to read this data before it is lost. Note that no zero de-stuffing is applied to the for the data provided through the RFDL register. The Receive FDL Register (RFDL) reports the incoming Facility Data Link (FDL) or the incoming Fs bits. The LSB is received first. In D4 framing mode, RFDL updates on multiframe boundaries and reports only the Fs bits.
9.9.6
E1 Datalink
FRAMER 1 ADDRESSES 64 65 66 67 69 to 6D 164 165 166 167 169 to 16D 114
The registers related to E1 Datalink is shown in the following table: REGISTER E1RAF E1RNAF E1RsiAF E1RSiNAF E1RSa4 to RSA8 E1TAF E1TNAF E1TSiAF E1TSiNAF E1TSa4 to TSA8 E1TSACR FUNCTION Receive Frame Alignment Register Receive Non-Frame Alignment Register Receive Si Bits of the Frame Alignment Frames Receive Si Bits of the Non-Frame Alignment Frames Receive Sa Bits Transmit Align Frame Register Transmit Non-Align Frame Register Transmit Si Bits of the Frame Alignment Frames Transmit Si Bits of the Non-Frame Alignment Frames Transmit Sa4 to Sa8 Transmit Source3 of Sa Control
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 - 8 can be calculated using the following: Framer N = (Framer 1 address + (n-1) x 200hex); where n = 2 to 8 for Framers 2 to 8.
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DS26528 Octal T1/E1/J1 Transceiver
9.9.6.1 Additional E1 Receive Sa and Si Bit Receive Operation (E1 Mode)
The DS26528, when operated in the E1 mode, provides for access to both the Sa and the Si bits via two methods. The first involves using the internal E1RAF/E1RNAF and E1TAF/E1TNAF registers. The second method involves an expanded version of the first method.
9.9.6.1.1 Internal Register Scheme Based On Double-Frame (Method 1)
On the receive side, the E1RAF and E1RNAF registers will always report the data as it received in the Sa and Si bit locations. The E1RAFand E1RNAF registers are updated on align frame boundaries. The setting of the Receive Align Frame bit in Latched Status Register 2 (RLS2.0) will indicate that the contents of the RAF and RNAF have been updated. The host can use the RLS2.0 bit to know when to read the E1RAF and E1RNAF registers. The host has 250ms to retrieve the data before it is lost.
9.9.6.1.2 Internal Register Scheme Based On CRC4 Multiframe
On the receive side, there is a set of eight registers (E1RsiAF, E1RSiNAF, E1RRA, E1RSa4 to E1RSa8) that report the Si and Sa bits as they are received. These registers are updated with the setting of the Receive CRC4 Multiframe bit in Latched Status Register 2 (RLS2.1). The host can use the RLS2.1 bit to know when to read these registers. The user has 2 ms to retrieve the data before it is lost. See the following register descriptions for additional information.
9.9.6.2 Internal Register Scheme Based On CRC4 Multiframe
On the transmit side there is a set of eight registers (E1TSiAF, E1TSiNAF, E1TRA, E1TSa4 to E1TSa8) that via the Transmit Sa Bit Control Register (E1TSACR), can be programmed to insert both Si and Sa data. Data is sampled from these registers with the setting of the Transmit Multiframe bit in Status Register 1 (TLS1.3). The host can use the TLS1.3 bit to know when to update these registers. It has 2ms to update the data or else the old data will be retransmitted. See the register descriptions below.
9.9.6.3 Sa Bit Monitoring and Reporting
In addition to the registers outlined above, the DS26528 provides status and interrupt capability in order to detect changes in the state of selected Sa bits. The E1RSAIMR register can be used to select which Sa bits are monitored for a change of state. When a change of state is detected in one of the enabled Sa bit positions, a status bit is set in the RLS7 register via the SaXCD bit (bit 0). This status bit can in turn be used to generate an interrupt by unmasking RIM7.0 (SaXCD). If multiple Sa bits have been enabled, the user can read the SABITS resigister at address 06Eh to determine the current value of each Sa bit. For the Sa6 bits, additional support is available to detect specific codewords per ETS300233. The Sa6CODE register will report the received Sa6 codeword. The codeword must be stable for a period of 3 sub-multiframes and be different from the previous stored value in order to be updated in this register Please see the Sa6CODE register description for further details on the operation of this register and the values reported in it. An additional status bit is provided in RLS7 (Sa6CD) to indicate if the received Sa6 codeword has changed. A mask bit is provided for this status bit in RIM7 to allow for interrupt generation when enabled.
9.9.7
Maintenance and Alarms
The DS26528 provides extensive functions for alarm detection and generation. It also provides diagnostic functions for monitoring of performance and sending of diagnostic information: * * * * * * * * Real-time and latched status bits, interrupts and interrupt mask for transmitter and receiver LOS detection RIA detection and generation PDV Violation detection Error counters DS0 Monitoring Milliwatt generation and detection Slip Buffer Status for Transmit and Receive
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DS26528 Octal T1/E1/J1 Transceiver Some of the Registers related to Maintenance and Alarms are as follows:
Table 9-22. Registers Related to Maintenance and Alarms
REGISTER Receive Real-Time Status Register 1 (RRTS1) Receive Interrupt Mask 1(RIM1) Receive Latched Status Register 2 (RLS2) Receive Real-Time Status Register 3 (RRTS3) Receive Latched Status Register 3 (RLS3) Receive Interrupt Mask Register 3 (RIM3) Receive Interrupt Mask Register 4 (RIM4) Rx Latched Status 7 (RLS7) Rx Interrupt Mask Reg 7 (RIM7) Tx Latched Status 1 (TLS1) Tx Latched Status 3 (SYNC)(TLS3) Rx DS0 Monitor (RDS0M) Rx Error Count Configuration (ERCNT) Line Code Violation Count Register 1 (LCVCR1) Line Code Violation Count Register 2 (LCVCR2) Path Code Violation Count Register 1 (PCVCR1) Path Code Violation Count Register 2 (PCVCR2) Frames Out Of Sync Count Register 1 (FOSCR1) Frames Out Of Sync Count Register 2 (FOSCR2) E1EBCR1 (E1EBCR1) E1EBCR2 (E1EBCR2) FRAMER 1 ADDRESSES 0B0 0A0 91 0B2 92 A2 A3 96 A6 190 192 060 086 050 051 052 053 054 055 056 057 FUNCTION Real-Time Receive Status 1 Real-Time Interrupt Mask 1 Real-Time Latched Status 2 Real-Time Receive Status 2 Real-Time Latched Status 3 Real-Time Interrupt Mask 3 Real-Time Interrupt Mask 3 Real-Time Latched Status 7 Real-Time Interrupt Mask 7 Loss of Transmit Clock Status, TPDV, etc. Loss of Frame Status Receive DS0 Monitor Configuration of the Error Counters Line Code Violation Counter Line Code Violation Counter Receive Path Code Violation Counter 1 Receive Path Code Violation Counter 2 Receive Frame Out of Sync Counter 1 Receive Frame Out of Sync Counter 2 E-Bit Count Register 1 E-Bit Count Register 2
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 - 8 can be calculated using the following: Framer N = (Framer 1 address + (n-1) x 200hex); where n = 2 to 8 for Framers 2 to 8.
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9.9.7.1 Status and Information Bit Operation
When a particular event has occurred (or is occurring), the appropriate bit in one of these registers will be set to a one. Status bits may operate in either a latched or real-time fashion. Some latched bits may be enabled to generate a hardware interrupt via the INTB signal. Real-Time Bits Some status bits operate in a real-time fashion. These bits are read-only and indicate the present state of an alarm or a condition. Real-time bits will remain stable, and valid during the host read operation. The current value of the internal status signals can be read at any time from the real-time status registers without changing any the latched status register bits Latched Bits When an event or an alarm occurs and a latched bit is set to a one, it will remain set until cleared by the user. These bits typically respond on a `change-of-state' for an alarm, condition, or event; and operate in a read-thenwrite fashion. The user should read the value of the desired status bit, and then write a `1' to that particular bit location in order to clear the latched value (write a `0' to locations not to be cleared). Once the bit is cleared, it will not be set again until the event has occurred again. Mask Bits Some of the alarms and events can be either masked or unmasked from the interrupt pin via the Interrupt Mask Registers (RIMx). When unmasked, the INTB signal will be forced low when the enabled event or condition occurs. The INTB pin will be allowed to return high (if no other unmasked interrupts are present) when the user reads then clears (with a write) the alarm bit that caused the interrupt to occur. Note that the latched status bit and the INTB pin will clear even if the alarm is still present. Note that some conditions may have multiple status indications. For example, Receive Loss of Frame (RLOF) provides the following indications: Real-time indication that the receiver is not synchronized with incoming data stream. Read-only bit that remains high as long as the condition is present. Latched indication that the receiver has loss synchronization since the bit was last cleared. Bit will clear when written by the user, even if the condition is still present (rising edge detect of RRTS1.0). Latched indication that the receiver has reacquired synchronization since the bit was last cleared. Bit will clear when written by the user, even if the condition is still present (falling edge detect of RRTS1.0).
RRTS1.0 (RLOF)
RLS1.0 (RLOFD)
RLS1.4 (RLOFC)
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Table 9-23. T1 Alarm Criteria
ALARM AIS (Blue Alarm) (see note 1 below) RAI (Yellow Alarm) 1. D4 bit 2 mode (T1RCR2.0 = 0) 2. D4 12th F-bit mode (T1RCR2.0 = 1; this mode is also referred to as the "Japanese Yellow Alarm") 3. ESF mode LOS Loss of Signal (this alarm is also referred to as Receive Carrier Loss (RCL)) SET CRITERIA when over a 3 ms window, 4 or less zeros are received when bit 2 of 256 consecutive channels is set to zero for at least 254 occurrences when the 12th framing bit is set to one for two consecutive occurrences when 16 consecutive patterns of 00FF appear in the FDL when 192 consecutive zeros are received CLEAR CRITERIA when over a 3 ms window, 5 or more zeros are received when bit 2 of 256 consecutive channels is set to zero for less than 254 occurrences when the 12th framing bit is set to zero for two consecutive occurrences when 14 or less patterns of 00FF hex out of 16 possible appear in the FDL when 14 or more ones out of 112 possible bit positions are received starting with the first one received
NOTES: 1. The definition of the Alarm Indication Signal (Blue Alarm) is an unframed all ones signal. AIS detectors should be able to operate properly in the presence of a 10E-3 error rate and they should not falsely trigger on a framed all ones signal. The AIS alarm criteria in the DS26528 has been set to achieve this performance. It is recommended that the RAIS bit be qualified with the RLOF bit. 2. The following terms are equivalent: RAIS = Blue Alarm RLOS = RCL RLOF = Loss of Frame (conventionally RLOS for Dallas Semiconductor devices) RRAI = Yellow Alarm
9.9.8
E1 Automatic Alarm Generation
The device can be programmed to automatically transmit AIS or Remote Alarm. When automatic AIS generation is enabled (TCR2.6 = 1), the device monitors the receive side framer to determine if any of the following conditions are present/ loss of receive frame synchronization, AIS alarm (all one's) reception, or loss of receive carrier (or signal). If any one (or more) of the above conditions is present, then the framer will either force an AIS. When automatic RAI generation is enabled (TCR2.5 = 1), the framer monitors the receive side to determine if any of the following conditions are present/ loss of receive frame synchronization, AIS alarm (all one's) reception, or loss of receive carrier (or signal) or if CRC4 multiframe synchronization cannot be found within 128ms of FAS synchronization (if CRC4 is enabled). If any one (or more) of the above conditions is present, then the framer will transmit a RAI alarm. RAI generation conforms to ETS 300 011 and ITU G.706 specifications. Note: It is an illegal state to have both automatic AIS generation and automatic Remote Alarm generation enabled at the same time.
9.9.8.1 Receive AIS-CI and RAI-CI Detection
AIS-CI is a repetitive pattern of 1.26 seconds. It consists of 1.11 seconds of an unframed all ones pattern and 0.15 seconds of all ones modified by the AIS-CI signature. The AIS-CI signature is a repetitive pattern 6176 bits in length in which, if the first bit is numbered bit 0, bits 3088, 3474 and 5790 are logical zeros and all other bits in the pattern are logical ones (T1.403). AIS-CI is an unframed pattern, so it is defined for all T1 framing formats. The RAIS-CI bit is set when the AIS-CI pattern has been detected and RAIS (RRTS1.2) is set. RAIS-CI is a latched bit that should be cleared by the host when read. RAIS-CI will continue to set approximately every 1.2 seconds that the condition is present. The host will need to `poll' the bit, in conjunction with the normal AIS indicators to determine when the condition has cleared. 59 of 269
DS26528 Octal T1/E1/J1 Transceiver RAI-CI is a repetitive pattern within the ESF data link with a period of 1.08 seconds. It consists of sequentially interleaving 0.99 seconds of "00000000 11111111" (right-to-left ) with 90 ms of "00111110 11111111". The RRAICI bit is set when a bit oriented code of "00111110 11111111" is detected while RRAI (RRTS1.3) is set. The RRAICI detector uses the receive BOC filter bits (RBF0 & RBF1) located in RBOCC to determine the integration time for RAI-CI detection. Like RAIS-CI, the RRAI-CI bit is latched and should be cleared by the host when read. RRAI-CI will continue to set approximately every 1.1 seconds that the condition is present. The host will need to `poll' the bit, in conjunction with the normal RAI indicators to determine when the condition has cleared. It may be useful to enable the 200ms ESF RAI integration time with the RAIIE control bit (T1RCR2.1) in networks that utilize RAI-CI.
9.9.8.2 T1 Receive Side Digital Milliwatt Code Generation
Receive side digital milliwatt code generation involves using the Receive Digital Milliwatt Registers (RDMR1/2/3) to determine which of the 24 T1 channels of the T1 line going to the backplane should be overwritten with a digital milliwatt pattern. The digital milliwatt code is an 8-byte repeating pattern that represents a 1kHz sine wave (1E/0B/0B/1E/9E/8B/8B/9E). Each bit in the RDMRx registers, represents a particular channel. If a bit is set to a one, then the receive data in that channel will be replaced with the digital milliwatt code. If a bit is set to zero, no replacement occurs.
9.9.9
Error Count Registers
The DS26528 contains four counters that are used to accumulate line coding errors, path errors and synchronization errors. Counter update options include one second boundaries, 42ms (T1 mode only), 62.5ms (E1 mode only) or manually. See Error Counter Configuration Register (ERCNT). When updated automatically, the user can use the interrupt from the timer to determine when to read these registers. All four counters will saturate at their respective maximum counts and they will not rollover (note: only the Line Code Violation Count Register has the potential to over-flow but the bit error would have to exceed 10E-2 before this would occur). The DS26528 can share the one-second timer from port #1 across all ports. All DS26528 error/performance counters can be configured to update on the shared one-second source, or a separate manual update signal input. See the ERCNT register for more information. By allowing multiple framer cores to synchronously latch their counters, the host software can be streamlined to read and process performance information from multiple spans in a more controlled manner.
9.9.9.1 Line Code Violation Count Register (LCVCR)
Either bipolar violations or code violations can be counted. Bipolar violations are defined as consecutive marks of the same polarity. In T1 mode, if the B8ZS mode is set for the receive side, then B8ZS codewords are not counted as BPVs. In E1 mode, if the HDB3 mode is set for the receive side, then HDB3 codewords are not counted as BPVs. If ERCNT.0 is set, then the LVC counts code violations as defined in ITU O.161. Code violations are defined as consecutive bipolar violations of the same polarity. In most applications, the framer should be programmed to count BPVs when receiving AMI code and to count CVs when receiving B8ZS or HDB3 code. This counter increments at all times and is not disabled by loss of sync conditions. The counter saturates at 65,535 and will not rollover. The bit error rate on an E1 line would have to be greater than 10E-2 before the VCR would saturate. See the following table for details of exactly what the LCVCRs count.
Table 9-24. T1 Line Code Violation Counting Options
COUNT EXCESSIVE ZEROS? (ERCNT.0) no yes no yes B8ZS ENABLED? (RCR1.6) no no yes yes WHAT IS COUNTED IN THE LCVCR1, LCVCR2 BPVs BPVs + 16 consecutive zeros BPVs (B8ZS/HDB3 codewords not counted) BPVs + 8 consecutive zeros
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Table 9-25. E1 Line Code Violation Counting Options
E1 CODE VIOLATION SELECT (ERCNT.0) 0 1 WHAT IS COUNTED IN THE LCVCRs BPVs CVs
9.9.9.2 Path Code Violation Count Register (PCVCR)
In T1 operation, the Path Code Violation Count Register records either Ft, Fs, or CRC6 errors. When the receive side of a framer is set to operate in the T1 ESF framing mode, PCVCR will record errors in the CRC6 codewords. When set to operate in the T1 D4 framing mode, PCVCR will count errors in the Ft framing bit position. Via the ERCNT.2 bit, a framer can be programmed to also report errors in the Fs framing bit position. The PCVCR will be disabled during receive loss of synchronization (RLOF = 1) conditions. See Table 9-26 for a detailed description of exactly what errors the PCVCR counts in T1 operation. In E1 operation, the Path Code Violation Count register records CRC4 errors. Since the maximum CRC4 count in a one second period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it will continue to count if loss of multiframe sync occurs at the CAS level. The Path Code Violation Count Register 1 (PCVCR1) is the most significant word and PCVCR2 is the least significant word of a 16-bit counter that records path violations (PVs).
Table 9-26. T1 Path Code Violation Counting Arrangements
FRAMING MODE D4 D4 ESF COUNT Fs ERRORS? no yes don't care WHAT IS COUNTED IN THE PCVCRs? errors in the Ft pattern errors in both the Ft & Fs patterns errors in the CRC6 codewords
9.9.9.3 Frames Out Of Sync Count Register (FOSCR)
The FOSCR is used to count the number of multiframes that the receive synchronizer is out of sync. This number is useful in ESF applications needing to measure the parameters Loss Of Frame Count (LOFC) and ESF Error Events as described in AT&T publication TR54016. When the FOSCR is operated in this mode, it is not disabled during receive loss of synchronization (RLOF = 1) conditions. The FOSCR has alternate operating mode whereby it will count either errors in the Ft framing pattern (in the D4 mode) or errors in the FPS framing pattern (in the ESF mode). When the FOSCR is operated in this mode, it is disabled during receive loss of synchronization (RLOF = 1) conditions. See Table 9-27 for a detailed description of what the FOSCR is capable of counting. In E1 mode, The FOSCR counts word errors in the Frame Alignment Signal in time slot 0. This counter is disabled when RLOF is high. FAS errors will not be counted when the framer is searching for FAS alignment and/or synchronization at either the CAS or CRC4 multiframe level. Since the maximum FAS word error count in a one second period is 4000, this counter cannot saturate. The Frames Out of Sync Count Register 1 (FOSCR1) is the most significant word and FOSCR2 is the least significant word of a 16-bit counter that records frames out of sync.
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Table 9-27. T1 Frames Out Of Sync Counting Arrangements
FRAMING MODE (RCR1.5) D4 D4 ESF ESF COUNT MOS OR F-BIT ERRORS (ERCNT.1) MOS F-Bit MOS F-Bit WHAT IS COUNTED IN THE FOSCR1 and FOSCR2 number of multiframes out of sync errors in the Ft pattern number of multiframes out of sync errors in the FPS pattern
9.9.9.4 E-Bit Counter (EBCR)
This counter is only available in E1 mode. E-bit Count Register 1 (E1EBCR1) is the most significant word and E1EBCR2 is the least significant word of a 16-bit counter that records Far End Block Errors (FEBE) as reported in the first bit of frames 13 and 15 on E1 lines running with CRC4 multiframe. These count registers will increment once each time the received E-bit is set to zero. Since the maximum E-bit count in a one second period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it will continue to count if loss of multiframe sync occurs at the CAS level.
9.9.10 DS0 Monitoring Function
The DS26528 can monitor one DS0 (64kbps) channel in the transmit direction and one DS0 channel in the receive direction at the same time. The registers related to the control of transmit and receive DS0 are shown in the following table.
Table 9-28. Registers Related to DS0 Monitoring
REGISTER TDS0SEL TDS0M RDS0SEL RDS0M FRAMER 1 ADDRESSES 189 1BB 012H 060H FUNCTION Transmit Channel to be Monitored The Monitored Data Receive Channel to be Monitored The Monitored Data
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 - 8 can be calculated using the following: Framer N = (Framer 1 address + (n-1) x 200hex); where n = 2 to 8 for Framers 2 to 8.
In the transmit direction the user will determine which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the TDS0SEL register. In the receive direction, the RCM0 to RCM4 bits in the RDS0SEL register need to be properly set. The DS0 channel pointed to by the TCM0 to TCM4 bits will appear in the Transmit DS0 Monitor (TDS0M) register and the DS0 channel pointed to by the RCM0 to RCM4 bits will appear in the Receive DS0 (RDS0M) register. The TCM4 to TCM0 and RCM4 to RCM0 bits should be programmed with the decimal decode of the appropriate T1or E1 channel. T1 channels 1 through 24 map to register values 0 through 23. E1 channels 1 through 32 map to register values 0 through 31. For example, if DS0 channel 6 in the transmit direction and DS0 channel 15 in the receive direction needed to be monitored, then the following values would be programmed into TDS0SEL and RDS0SEL: TCM4 = 0 RCM4 = 0 TCM3 = 0 RCM3 = 1 TCM2 = 1 RCM2 = 1 TCM1 = 0 RCM1 = 1 TCM0 = 1 RCM0 = 0
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9.9.11 Transmit Per-Channel Idle Code Insertion
Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. The Transmit Idle Definition Registers (TIDR1-TIDR32) are provided to set the 8-bit idle code for each channel. The Transmit Channel Idle Code Enable registers (TCICE1-4) are used to enable idle code replacement on a per channel basis.
9.9.12 Receive Per-Channel Idle Code Insertion
Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. The Receive Idle Definition Registers (RIDR1-RIDR32) are provided to set the 8-bit idle code for each channel. The Receive Channel Idle Code Enable registers (RCICE1-4) are used to enable idle code replacement on a perchannel basis.
9.9.13 Per-Channel Loopback
The Per-Channel Loopback Registers (PCL1 to PCL4) determine which channels (if any) from the backplane should be replaced with the data from the receive side or in other words, off of the T1 or E1 line. If this loopback is enabled, then transmit and receive clocks and frame syncs must be synchronized. One method to accomplish this would be to tie RCLK to TCLK and RFSYNC to TSYNC. There are no restrictions on which channels can be looped back or on how many channels can be looped back. Each of the bit positions in the Per-Channel Loopback Registers (PCL1/PCLR2/PCLR3/ PCLR4) represent a DS0 channel in the outgoing frame. When these bits are set to a one, data from the corresponding receive channel will replace the data on TSER for that channel.
9.9.14 E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only)
The DS26528 can implement the G.706 CRC-4 recalculation at intermediate path points. When this mode is enabled, the data stream presented at TSER will already have the FAS/NFAS, CRC multiframe alignment word and CRC-4 checksum in time slot 0. The user can modify the Sa bit positions and this change in data content will be used to modify the CRC-4 checksum. This modification however will not corrupt any error information the original CRC-4 checksum may contain. In this mode of operation, TSYNC must be configured to multiframe mode. The data at TSER must be aligned to the TSYNC signal. If TSYNC is an input then the user must assert TSYNC aligned at the beginning of the multiframe relative to TSER. If TSYNC is an output, the user must multiframe align the data presented to TSER. This mode is enabled with the TCR3.0 control bit (CRC4R). Note that the E1 transmitter must already be enabled for CRC insertion with the TCR1.0 control bit (TCRC4).
Figure 9-15. CRC-4 Recalculate Method
TPOSO/TNEGO
INSERT NEW CRC-4 CODE
EXTRACT OLD CRC-4 CODE
TSER
+
CRC-4 CALCULATOR
XOR
MODIFY Sa BIT POSITIONS
NEW Sa BIT DATA
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9.9.15 T1 Programmable In-Band Loop Code Generator
The DS26528 can generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode.
Table 9-29. Registers Related to T1 In-Band Loop Code Generator
REGISTER T1TCD1 T1TCD2 TCR3 TCR4 FRAMER 1 ADDRESSES 1AC 1AD 183 186 FUNCTION Pattern to be sent for Loop Code Length of the pattern to be sent TLOOP bit for control of number of patterns being sent Length of the code being sent
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 - 8 can be calculated using the following: Framer N = (Framer 1 address + (n-1) x 200hex); where n = 2 to 8 for Framers 2 to 8.
To transmit a pattern, the user will load the pattern to be sent into the Transmit Code Definition registers (TCD1&TCD2) and select the proper length of the pattern by setting the TC0 and TC1 bits in Transmit Control Register 4 (TCR4). When generating a 1-, 2-, 4-, 8-, or 16-bit pattern both transmit code definition registers (TCD1&TCD2) must be filled with the proper code. Generation of a 3-, 5-, 6-, and 7-bit pattern only requires TCD1 to be filled. Once this is accomplished, the pattern will be transmitted as long as the TLOOP control bit (TCR3.0) is enabled. Normally (unless the transmit formatter is programmed to not insert the F-bit position) the framer will overwrite the repeating pattern once every 193 bits to allow the F-bit position to be sent. As an example, to transmit the standard "loop up" code for Channel Service Units (CSUs), which is a repeating pattern of ...10000100001..., set TCD1 = 80h, TC0=0, TC1=0, and TCR3.0 = 1.
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9.9.15.1 T1 Programmable In-Band Loop Code Detection
The DS26528 can generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode.
Table 9-30. Registers Related to T1 In-Band Loop Code Detection
REGISTERS RELATED T1 IN-BAND LOOP CODE DETECTION Receive In-Band Code Control Register (T1RIBCC) Receive Up Code Definition Register 1 (T1RUPCD1) Receive Up Code Definition Register 1 (T1RUPCD2) Receive Down Code Definition Register 1 (T1RDNCD1) Receive Down Code Definition Register 2 (T1RDNCD2) Receive Spare Code Register 1 (T1RSCD1) Receive Spare Code Register 1 (T1RSCD2) Receive Real-Time Status Register 3 (RRTS3) Receive Latched Status Register 3 (RLS3) Receive Interrupt Mask Register 3 (RIM3) FRAMER 1 ADDRESSES 82 AC AD AE AF 9C 9D B2 B3 B4 FUNCTION Used for Selecting Length of Receive InBand Loop Code Register Receive Up Code Definition Register 1 Receive Up Code Definition Register 2 Receive Down Code Definition Register 1 Receive Up Code Definition Register 2 Receive Spare Code Register Receive Spare Code Register Real-Time Loop Code Detect Latched Loop Code Detect Bits Mask for Latched Loop Code Detect Bits
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 - 8 can be calculated using the following: Framer N = (Framer 1 address + (n-1) x 200hex); where n = 2 to 8 for Framers 2 to 8.
The framer has three programmable pattern detectors. Typically, two of the detectors are used for "loop up" and "loop down" code detection. The user will program the codes to be detected in the Receive Up Code Definition (RUPCD1 and RUPCD2) registers and the Receive Down Code Definition (RDNCD1 and RDNCD2) registers and the length of each pattern will be selected via the RIBCC register. There is a third detector (Spare) and it is defined and controlled via the RSPCD1/RSPCD2 and RSCC registers. When detecting a 16-bit pattern both receive code definition registers are used together to form a 16-bit register. For 8-bit patterns both receive code definition registers will be filled with the same value. Detection of a 1-, 2-, 3-, 4-, 5-, 6-, and 7-bit pattern only requires the first receive code definition register to be filled. The framer will detect repeating pattern codes in both framed and unframed circumstances with bit error rates as high as 10E-2. The detectors are capable of handling both F-bit inserted and F-bit overwrite patterns. Writing the least significant byte of receive code definition register resets the integration period for that detector. The code detector has a nominal integration period of 48ms. Hence, after about 48ms of receiving a valid code, the proper status bit (LUP, LDN, and LSP) will be set to a one. Note that real-time status bits, as well as latched set and clear bits are available for LUP, LDN and LSP (RRTS3 and RLS3). Normally codes are sent for a period of 5 seconds. It is recommend that the software poll the framer every 50ms to 100ms until 5 seconds has elapsed to ensure that the code is continuously present.
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9.9.16 Framer Payload Loopbacks
The framer, payload and remote loopbacks are controlled by RCR3.
Table 9-31. Register Related to Framer Payload Loopbacks
RECEIVE CONTROL REGISTER 3 (RCR3) Framer Loopback Payload Loopback Remote Loopback FRAMER 1 ADDRESSES 083 083 083 FUNCTION Transmit data output from the framer is looped back to the receiver The 192-bit payload data is looped back to the Transmitter Data recovered by the Receiver is looped back to the transmitter
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 - 8 can be calculated using the following: Framer N = (Framer 1 address + (n-1) x 200hex); where n = 2 to 8 for Framers 2 to 8.
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9.10 HDLC Controllers
9.10.1 Receive HDLC Controller
This device has an enhanced HDLC controller that can be mapped into a single time slot, or Sa4 to Sa8 bits (E1 Mode) or the FDL (T1 Mode). The HDLC controller has 64-byte FIFO buffer in both the transmit and receive paths. The user can select any specific bits within the time slot(s) to assign to the HDLC controller, as well as specific Sa bits (E1 Mode) The HDLC controller performs all the necessary overhead for generating and receiving Performance Report Messages (PRM) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The HDLC controller automatically generates and detects flags, generates and checks the CRC check sum, generates and detects abort sequences, stuffs and de-stuffs zeros, and byte aligns to the data stream. The 64-byte buffers in the HDLC controller are large enough to allow a full PRM to be received or transmitted without host intervention. The registers related to the HDLC are displayed in the following table. FRAMER 1 ADDRESSES 010 011 087 0B5 0B6 0B4 094 0A4 110 111 113 187 1B1 191 1A1 1B3 1B4
REGISTER Receive HDLC Control Register (RHC) Receive HDLC Bit Suppress Register (RHBSE) Receive HDLC FIFO Control (RHFC) Receive HDLC Packet Bytes Available Register (RHPBA) Receive HDLC FIFO Register (RHF) Receive Real-Time Status Register 5 (RRTS5) Receive Latched Status Register 5 (RLS5) Receive Interrupt Mask 5 (RIM5) Transmit HDLC Control 1(THC1) Transmit HDLC Bit Suppress (THBSE) Transmit HDLC Control 2 (THC2) Transmit HDLC FIFO Control (THFC) Transmit HDLC Status (TRTS2) Transmit HDLC Latched Status (TLS2) Transmit Interrupt Mask Register 2 (TIM2) Transmit HDLC FIFO Buffer Available (TFBA) Transmit HDLC FIFO (THF)
FUNCTION Mapping of the HDLC to DS0 or FDL Receive HDLC bit suppression Register Determines the length of the Receive HDLC FIFO Tells the user how many bytes are available in the Receive HDLC FIFO The actual FIFDO data Indicates the FIFO status Latched Status Interrupt Mask for interrupt generation for the Latched Status Misc Transmit HDLC Control Transmit HDLC Bit Suppress for bits not to be used HDLC to DS0 channel selection and other control Used to control the Transmit HDLC FIFO Indicates the Real-Time Status of the Transmit HDLC FIFO Indicates the FIFO status Interrupt Mask for the Latched Status Indicates the number of bytes that can be written into the Transmit FIFO Transmit HDLC FIFO
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 - 8 can be calculated using the following: Framer N = (Framer 1 address + (n-1) x 200hex); where n = 2 to 8 for Framers 2 to 8.
9.10.1.1 HDLC FIFO Control
Control of the transmit and receive FIFOs is accomplished via the Receive HDLC FIFO Control (RHFC) and Transmit HDLC FIFO Control (THFC) registers. The FIFO Control registers set the watermarks for the FIFO. When the receive FIFO fills above the high watermark, the RHWM bit (RRTS5.1) will be set. RHWM and THRM are real-time bits and will remain set as long as the FIFO's write pointer is above the watermark. When the transmit FIFO empties below the low watermark, the TLWM bit in the TRTS2 register will be set. TLWM is a real-time bit 67 of 269
DS26528 Octal T1/E1/J1 Transceiver and will remain set as long as the transmit FIFO's write pointer is below the watermark. If enabled, this condition can also cause an interrupt via the INTB pin. If the receive HDLC FIFO does overrun the current packet being processed is dropped. The receive FIFO is emptied . The packet status bit in RRTS5 and RLS5.5 (ROVR) indicate an overrun.
9.10.1.2 Receive Packet Bytes Available
The lower 7 bits of the Receive Packet Bytes Available register indicates the number of bytes (0 through 64) that can be read from the receive FIFO. The value indicated by this register informs the host as to how many bytes can be read from the receive FIFO without going past the end of a message. This value will refer to one of four possibilities, the first part of a packet, the continuation of a packet, the last part of a packet, or a complete packet. After reading the number of bytes indicated by this register the host then checks the HDLC Status registers for detailed message status. If the value in the RHPBA register refers to the beginning portion of a message or continuation of a message then the MSB of the RHPBA register will return a value of 1. This indicates that the host may safely read the number of bytes returned by the lower 7 bits of the RHPBA register but there is no need to check the information register since the packet has not yet terminated (successfully or otherwise).
9.10.1.3 HDLC Status And Information
RRTS5, RLS5, and TLS2 provide status information for the HDLC controller. When a particular event has occurred (or is occurring), the appropriate bit in one of these registers will be set to a one. Some of the bits in these registers are latched and some are real-time bits that are not latched. This section contains register descriptions that list which bits are latched and which are real-time. With the latched bits, when an event occurs and a bit is set to a one, it will remain set until the user reads and clears that bit. The bit will be cleared when a `1' is written to the bit and it will not be set again until the event has occurred again. The real-time bits report the current instantaneous conditions that are occurring and the history of these bits is not latched. Like the other latched status registers, the user will follow a read of the status bit with a write. The byte written to the register will inform the device which of the latched bits the user wishes to clear (the real-time bits are not affected by writing to the status register). The user will write a byte to one of these registers, with a one in the bit positions he or she wishes to clear and a zero in the bit positions he or she does not wish to clear. The HDLC status registers RLS5 and TLS2 have the ability to initiate a hardware interrupt via the INTB output signal. Each of the events in this register can be either masked or unmasked from the interrupt pin via the HDLC Interrupt Mask Registers RIM5 and TIM2. Interrupts will force the INTB signal low when the event occurs. The INTB pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur.
9.10.1.4 HDLC Receive Example
The HDLC status registers in the DS26528 allow for flexible software interface to meet the user's preferences. When receiving HDLC messages, the host can chose to be interrupt driven, or to poll to desired status registers, or a combination of polling and interrupt processes may be used. An example routine for using the DS26528 HDLC receiver is given in the following figure.
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Figure 9-17. Receive HDLC Example
Configure Receive HDLC Controller (RHC, RHBSE, RHFC)
Reset Receive HDLC Controller (RHC.6)
Start New Message Buffer
Enable Interrupts RPE and RHWM
Interrupt?
NO
No Action Required Work Another Process.
YES Read Register RHPBA
Start New Message Buffer
NO
MS = 1?
(MS = RHPBA[7])
YES
Read N Bytes From Rx HDLC FIFO (RHF) N = RHPBA[5..0]
Read N Bytes From Rx HDLC FIFO (RHF) N = RHPBA[5..0]
Read RRTS5 for Packet Status (PS2..0) Take appropriate action
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9.10.2 Transmit HDLC Controller 9.10.3 FIFO Information
The Transmit FIFO Buffer Available register (TFBA) indicates the number of bytes that can be written into the transmit FIFO. The count form this register informs the host as to how many bytes can be written into the transmit FIFO without overflowing the buffer. This is a real-time register. The count shall remain valid and stable during the read cycle.
9.10.4 HDLC Transmit Example
The HDLC status registers in the DS26528 allow for flexible software interface to meet the user's preferences. When transmitting HDLC messages, the host can choose to be interrupt driven, or to poll to desired status registers, or a combination of polling and interrupt processes may be used. An example routine for using the DS26528 HDLC receiver is given in the following figure.
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Figure 9-19. HDLC Message Transmit Example
Configure Transmit HDLC Controller
(THC1,THC2,THBSE,THFC)
Reset Transmit HDLC Controller (THC.5)
Enable TLWM Interrupt and Verify TLWM Clear
Set TEOM (THC1.2)
Read TFBA N = TFBA[6..0]
Push Last Byte into Tx FIFO
Push Message Byte into Tx HDLC FIFO (THF) Loop N Last Byte of Message? NO TLWM Interrupt? YES NO NO YES
Enable TMEND Interrupt
TMEND Interrupt? YES Read TUDR Status Bit
NO
A
A
TUDR = 1
A
YES No Action Required Work Another Process
Disable TMEND Interrupt Prepare New Message Disable TMEND Interrupt Resend Message
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9.11 Line Interface Units (LIU)
The DS26528 has eight identical LIU transmit and receive front ends for each of the eight framers. Each LIU contains three sections: the transmitter, which waveshapes and drives the network line; the receiver, which handles clock and data recovery; and the jitter attenuator. The DS26528 LIUs can switch between T1 or E1 networks without changing any external components on either the transmit or receive side. Figure 9-21 shows a recommended circuit for software selected termination with protection. In this configuration the device can connect to 100W T1 twisted pair, 110W J1 twisted pair, 75W or 120W E1 twisted pair without additional component changes. The signals between the framer and LIU are not accessible by the user, thus the framer and LIU cannot be separated. The transmitters have fast High-Z capability and can be individually powered down. The DS26528's transmit waveforms meet the corresponding G.703 and T1.102 specifications. Internal softwareselectable transmit termination is provided for 100W T1 twisted pair, 110W J1 twisted pair, 120W E1 twisted pair and 75W E1 coaxial applications. The receiver can connect to 100W T1 twisted pair, 110W J1 twisted pair, 120W E1 twisted pair, and 75W E1 coaxial. The receive LIU can function with a receive signal attenuation of up to 36dB for T1 mode and 43dB for E1 mode. The receiver sensitivity is programmable from 12dB to 43dB of cable loss. Also a monitor gain setting can be enabled to provide 14, 20, 26 and 32dB of resistive gain.
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Figure 9-21. Network Connection for Software Selected Termination, Longitudinal Protection
NAME
F1 to F4 S1, S2 S3, S4, S5, S6 S7, S8 T1 and T2 T1 and T2 T3 and T4
DESCRIPTION
1.25A Slow Blow Fuse 1.25A Slow Blow Fuse 25V (max) Transient Suppressor 180V (max) Transient Suppressor 40V (max) Transient Suppressor Transformer 1:1CT and 1:136CT (5.0V, SMT) Transformer 1:1CT and 1:2CT (3.3V, SMT) Dual Common-Mode Choke (SMT)
PART
SMP 1.25 F1250T P0080SA MC P1800SC MC P0300SC MC T1136 PE-68678 PE-65857
MANUFACTURER
Bel Fuse Teccor Electronics Teccor Electronics Teccor Electronics Teccor Electronics Pulse Engineering Pulse Engineering Pulse Engineering
Notes
5 5 1, 5 1, 4, 5 1, 5 2, 3, 5 2, 3, 5 5
Note 1: Changing S7 and S8 to P1800SC devices provides symmetrical voltage suppresion between Tip, Ring, and Ground. Note 2: The layout from the transformers to the network interface is critical. Traces should be at least 25 mils wide and separated from other circuit lines by at least 150 mils. The area under this portion of the circuit should not contain power planes. Note 3: Some T1 (never in E1) applications source or sink power from the network-side center taps of the Rx/Tx transformers. Note 4: The Ground trace connected to the S2/S3 pair and the S4/S5 pair should be at least 50 mils wide to conduct the extra current from a longitudinal power-cross event. Note 5: Alternative component recommendations and line interface circuits can be found by contacting telecom.support@dalsemi.com or in Application Note 324, which is available at www.maxim-ic.com
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Figure 9-23. Recommended Supply Decoupling
SUPPLY PINS DVDD / DVSS DVDDIO / DVSSIO DECOUPLING CAPACITANCE 0.01mF + 0.1mF + 1mF + 10mF 0.01mF + 0.1mF + 1mF + 10mF It is recommended to use one 0.1mF cap for each ATVDD/ATVSS pair (8 total), one 1mF for every two ATVDD/ATVSS pairs (4 total), and two 10mF capacitors for the analog transmit supply pins. These capcitors should be located as close to the intended power pins as possible. It is recommended to use one 0.1mF cap for each ARVDD/ARVSS pair (8 total), one 1mF for every two ARVDD/ARVSS pairs (4 total), and two 10mF capacitors for the analog receive supply pins. These capcitors should be located as close to the intended power pins as possible. NOTES
ATVDD / ATVSS
0.1mF (x8) + 1mF (x4) + 10mF (x2)
ARVDD / ARVSS
0.1mF (x8) + 1mF (x4) + 10mF (x2)
ACVDD / ACVSS
0.1mF + 1mF + 10mF
9.11.1 LIU Operation
The analog AMI/HDB3 waveforms off of the E1 lines or the AMI/B8ZS waveform off of the T1 lines are transformer coupled into the RTIP and RRING pins of the DS26528. The user has the option to use internal termination, software selectable for 75W/100W/110W/120W applications, or external termination. The LIU recovers clock and data from the analog signal and passes it through the jitter attenuation mux. The DS26528 contains an active filter that reconstructs the analog received signal for the nonlinear losses that occur in transmission. The receive circuitry also is configurable for various monitor applications. The device has a usable receive sensitivity of 0dB to -43dB for E1 and 0dB to -36dB for T1, which allows the device to operate on 0.63mm (22AWG) cables up to 2.5km (E1) and 6k feet (T1) in length. Data input to the transmit side of the LIU is sent via the jitter attenuation MUX to the wave shaping circuitry and line driver. The DS26528 will drive the E1 or T1 line from the TTIP and TRING pins via a coupling transformer. The line driver can handle both CEPT 30/ISDN-PRI lines for E1 and long-haul (CSU) or short-haul (DSX-1) lines for T1. The registers that control the LIU operation are shown in Table 9-32.
Table 9-32. Registers Related to Control of DS26528 LIU
REGISTER GTCR2 - Global Transceiver Control Register 2 GTCCR Global Transceiver Clock Control Register GLSRR Global LIU Reset Register Control GLISR Global LIU Interrupt Status Register GLIMR Global LIU Interrupt Mask Register LTRCR LIU Transmit Receive Control Register LTITSR LIU Transmit Impedance Selection Register
LMCR LIU Maintenance Register LRSR LIU Real Status Register LSIMR LIU Status Interrupt Mask
ADDRESS (HEX)
00F2 00F3 00F5 00FB 00FE 1000, 1020, 1040, 1060, 1080, 10A0, 10C0, 10E0 1001, 1021, 1041, 1061, 1081, 10A1, 10C1, 10E1 1002, 1022, 1042, 1062, 1082, 10A2, 10C2, 10E2 1003,1023,1043,1063,1083,10A3, 10C3, 10E3 1004,1024,1044,1064,1084,10A4,
FUNCTION
Global Transceiver Control MPS Selections, Backplane Clock Selections Software reset control for the LIU Interrupt Status bit for each of the 8 LIUs Interrupt Mask Register for the LIU T1J1 E1 selection, Output Tri-state, Loss Criteria Transmit Pulse Shape and Impedance Selection Trans Maintenance and Jitter Attenuation Control Register LIU Real-Time Status Register LIU Mask Registers based on Latched
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Register LLSR LIU Latched Status Register LRSL LIU Receive Signal Level LRISMR LIU Receive Impedance and Sensitivity Monitor Register 10C4, 10E4 1005,1025,1045,1065,1085,10A5, 10C5, 10E5 1006,1026,1046,1066,1086,10A6, 10C6, 10E6 1007,1027,1047,1067,1087,10A7, 10C7, 10E7 Status Bits LIU latched status bits related to loss, Open circuit, etc. LIU Receive Signal Level Indicator LIU Impedance Match and Sensitivity Monitor
9.11.2 Transmitter
NRZ data arrives from the framer transmitter; the data is encoded with HDB3 or B8ZS or AMI. The encoded data passes through a jitter attenuator if it is enabled for the transmit path. A digital sequencer and DAC are used to generate transmit waveforms complaint with T1.102 and G.703 pulse templates. A line driver is used to drive an internal matched impedance circuit for provision of 75W, 100W, 110W, and 120W terminations. The transmitter couples to the E1 or T1 transmit twisted pair (or coaxial cable in some E1 applications) via a 1:2 step-up transformer. In order for the device to create the proper waveforms, the transformer used must meet the specifications listed in Table 9-34. The transmitter requires a transmit clock of 2.048MHz for E1 or 1.544MHz for T1/J1 operation. The DS26528 drivers have a short circuit and open circuit detection driver fail monitor. There is a TXEnable pin that can High-Z the transmitter outputs for protection switching. The individual transmitters can also be placed in High-Z through register settings. The DS26528 also has functionality for powering down the transmitters individually. The relevant telecommunications specification compliance is shown in Table 9-33.
Table 9-33. The Telecommunications Specification Compliance for DS26528 Transmitters
TRANSMITTER FUNCTION T1 Telecom Pulse Template Compliance T1 Telecom Pulse Template Compliance Transmit Electrical Characteristics for E1 Transmission and Return Loss Compliance TELECOMMUNICATIONS COMPLIANCE ANSI T1.403 ANSI T1.102 ITUT G.703
Table 9-34. Transformer Specifications
SPECIFICATION Turns Ratio 3.3V Applications Primary Inductance Leakage Inductance Intertwining Capacitance Transmit Transformer DC Resistance Primary (Device Side) Secondary Receive Transformer DC Resistance Primary (Device Side) Secondary RECOMMENDED VALUE 1:1 (receive) and 1:2 (transmit) 2% 600mH minimum 1.0mH maximum 40pF maximum 1.0W maximum 2.0W maximum 1.2W maximum 1.2W maximum
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9.11.2.1 Transmit Line Pulse Shapes
The DS26528 transmitters can be selected individually to meet the pulse templates for E1 and T1/J1 modes. The T1/J1 pulse template is shown in Figure 9-25. The E1 pulse template is shown in Figure 9-27. The transmit pulse shape can be configured for each LIU on an individual basis. The LIU transmit impedance selection registers can be used to select an internal transmit terminating impedance of 100W for T1, 110W for J1 mode, 75W or 120W for E1 mode or no internal termination for E1 or T1 mode. The transmit pulse shape and terminating impedance is selected by LTITSR registers. The pulse shapes will be complaint to T1.102 and G.703. Pulse shapes are measured for compliance at the appropriate network interface (NI). For T1 long haul and E1, the pulse shape is measured at the far end. For T1 short haul, the pulse shape is measured at the near end.
Figure 9-25. T1/J1 Transmit Pulse Templates
1.2 1.1 1.0 0.9 0.8 0.7
NORMALIZED AMPLITUDE
0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -500 -400 -300 -200 -100 0 100 200 TIME (ns) 300 400 500 600 700
T1.102/87, T1.403, CB 119 (Oct. 79), & I.431 Template
DSX-1 Template (per ANSI T1.102 1993) MINIMUM CURVE MAXIMUM CURVE
UI -0.77 -0.39 -0.27 -0.27 -0.12 0.00 0.27 0.35 0.93 1.16 Time -500 -255 -175 -175 -75 0 175 225 600 750 Amp. 0.05 0.05 0.80 1.15 1.15 1.05 1.05 -0.07 0.05 0.05 UI -0.77 -0.23 -0.23 -0.15 0.00 0.15 0.23 0.23 0.46 0.66 0.93 1.16 Time -500 -150 -150 -100 0 100 150 150 300 430 600 750 Amp. -0.05 -0.05 0.50 0.95 0.95 0.90 0.50 -0.45 -0.45 -0.20 -0.05 -0.05
DS1 Template (per ANSI T1.403 1995)
MAXIMUM CURVE UI Time Amp. -0.77 -0.39 -0.27 -0.27 -0.12 0.00 0.27 0.34 0.77 1.16 -500 -255 -175 -175 -75 0 175 225 600 750 0.05 0.05 0.80 1.20 1.20 1.05 1.05 -0.05 0.05 0.05 -0.77 -0.23 -0.23 -0.15 0.00 0.15 0.23 0.23 0.46 0.61 0.93 1.16
MINIMUM CURVE UI Time Amp. -500 -150 -150 -100 0 100 150 150 300 430 600 750 -0.05 -0.05 0.50 0.95 0.95 0.90 0.50 -0.45 -0.45 -0.26 -0.05 -0.05
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Figure 9-27. E1 Transmit Pulse Templates
1.2 1.1 1.0
(in 75 ohm systems, 1.0 on the scale = 2.37Vpeak in 120 ohm systems, 1.0 on the scale = 3.00Vpeak) 269ns
0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2
-250 -200 -150 -100 -50 0 50 100 150 200 250 219ns 194ns
SCALED AMPLITUDE
G.703 Template
TIME (ns)
9.11.2.2 Transmit Power-Down
The individual transmitters can be powered down by setting the TPDE bit in the LIU maintenance control register (LMCR). Note that powering down the transmit LIU results in a High-Z state for the corresponding TTIP and TRING pins. When Transmit all ones (AIS) is invoked, continuous ones are transmitted using MCLK as the timing reference. Data input from the framer is ignored. AIS can be sent by setting a bit in the LIU maintenance control register (LMCR). Transmit all ones will also be sent if the corresponding receiver goes into LOS state and the ATAIS bit is set in the LIU maintenance control register.
9.11.2.3 Transmit Short-Circuit Detector/Limiter
Each transmitter has an automatic short-circuit current limiter that activates when the load resistance is approximately 25W or less. SCS (LRSR) provides a real-time indication of when the current limiter is activated. LIU Latched Status Register (LLSR) provides a latched versions of the information, which can be used to activate an interrupt when enable via the LSIMR register.
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9.11.2.4 Transmit Open-Circuit Detector
The DS26528 can also detect when the TTIP or TRING outputs are open circuited. OCS (LRSR) will provide a realtime indication of when an open circuit is detected. Register LLSR provides latched versions of the information, which can be used to activate an interrupt when enabled via the LSIMR register. The open circuit detect feature is not available in T1 CSU operating modes (LBO 5, LBO6 and LBO7).
9.11.3 Receiver
The DS26528 contains eight identical receivers. All receivers are designed to be fully software-selectable for E1, T1, and J1 without the need to change any external resistors. The device couples to the receive E1 or T1 twisted pair (or coaxial cable in 75W E1 applications) via a 1:1 or 2:1 transformer. See Table 9-34 for transformer details. Receive termination and sensitivity are user configurable. Receive termination is configurable for 75W, 100W, 110W, or 120W termination by setting the appropriate RIMPM[1:0] bits (LRISMR). When using the internal termination feature, the resistors labeled Rr in Figure 9-21 should be 60W each. If external termination is required, the resistors will need to be 37.5W, 50W, or 60W each depending on the line impedance. Receive sensitivity is configurable by setting the appropriate RSMS[1:0] bits (LRISMR). The DS26528 uses a digital clock recovery system. The resultant E1, T1 or J1 clock derived from MCLK is multiplied by 16 via an internal PLL and fed to the clock recovery system. The clock recovery system uses the clock from the PLL circuit to form a 16 times over-sampler, which is used to recover the clock and data. This oversampling technique offers outstanding performance to meet jitter tolerance specifications shown in Table 9-16. Normally, the clock that is output at the RCLK pin is the recovered clock from the E1 AMI/HDB3 or T1 AMI/B8ZS waveform presented at the RTIP and RRING inputs. If the jitter attenuator (LTRCR) is placed in the receive path (as is the case in most applications), the jitter attenuator restores the RCLK to an approximate 50% duty cycle. If the jitter attenuator is either placed in the transmit path or is disabled, the RCLK output can exhibit slightly shorter high cycles of the clock. This is due to the highly over-sampled digital clock recovery circuitry. See the Receiver AC Characteristics section for more details. When no signal is present at RTIP and RRING, a receive carrier loss (RCL) condition will occur and the RCLK will be derived from the JACLK source
9.11.3.1 Receive Level Indicator
The DS26528 will report the signal strength at RTIP and RRING in approximately 2.5dB increments via RSL3RSL0 located in the LIU receive signal level register (LRSL). This feature is helpful when trouble shooting line performance problems.
9.11.3.2 Receive G.703 Section 10 Synchronization Signal
The DS26528 is capable of receiving a 2.048MHz square-wave synchronization clock as specified in Section 10 of ITU G.703. In order to use this mode, set the Receive G.703 Clock Enable found in LIU Receive Impedance and Sensitivity Monitor Register (LRISMR).
9.11.3.3 Receiver Monitor Mode
The receive equalizer is equipped with a monitor mode function that is used to overcome the signal attenuation caused by the resistive bridge used in monitoring applications. This function allows for a resistive gain of up to 32dB along with cable attenuation of 12dB to 30dB as shown in LIU Receive Impedance and Sensitivity Monitor Register (LRISMR).
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Figure 9-29. Typical Monitor Application
PRIMARY T1/E1 TERMINATING DEVICE Rm
X F M R
T1/E1 LINE
Rm
Rt
DS26528
MONITOR PORT JACK
SECONDARY T1/E1 TERMINATING DEVICE
9.11.3.4 Loss of Signal
The DS26528 uses both the digital and analog loss detection method in compliance with the latest T1.231 for T1/J1 and ITU G.775 or ETSI 300 233 for E1 mode of operation. LOS is detected if the receiver level falls bellow a threshold analog voltage for certain duration. Alternatively, this can be termed as having received "zeros" for a certain duration. The signal level and timing duration are defined in accordance with the T1.231 or G.775 or ETSI 300 233 specifications. For short haul mode, the loss detection thresholds are based on cable loss of 12dB to 18dB for both T1/J1 and E1 modes. The loss thresholds are selectable based on Table 10-18. For long-haul mode, the LOS Detection threshold is based on cable loss of 30dB to 38dB for T1/J1 and 30dB to 45dB for E1 mode. Note there is no explicit bit called short haul mode selection. Loss declaration level is set at 3dB lower that the maximum sensitivity setting programmed in Table 10-18. The loss state is exited when the receiver detects a certain ones density at the maximum sensitivity level or higher, which is 3dB higher than the loss detection level. The loss detection signal level and loss reset signal level are defined with hysteresis to prevent the receiver from bouncing between "LOS" and "no LOS" states. Table 9-35 outlines the specifications governing the loss function.
Table 9-35. T1.231, G.775, and ETSI 300 233 Loss Criteria Specifications
CRITERIA Loss Detection T1.231 No pulses are detected for 175 75 bits. Loss is terminated if a duration of 12.5% ones are detected over duration of 175 75 bits. Loss is not terminated if 8 consecutive zeros are found if B8ZS encoding is used. If B8ZS is not used loss is not terminated if 100 consecutive pulses are zero. STANDARD ITU G.775 No pulses are detected for duration of 10 to 255 bit periods. The incoming signal has transitions for duration of 10 to 255 bit periods. ETSI 300 233 No pulses are detected for a duration of 2048 bit periods or 1ms Loss reset criteria is not defined.
Loss Reset
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9.11.3.5 ANSI T1.231 for T1 and J1 Modes
For short haul mode, loss is declared if the received signal level is 3dB lower from the programmed value (based on Table 10-18 for a duration of 192-bit periods. Hence if the sensitivity is programmed to be 12dB, loss will be declared at 15dB. LOS is reset if all of the following criteria are met: * * 24 or more ones are detected in 192-bit period with a programmed sensitivity level measured at RTIP and RRING. During the 192 bits less than 100 consecutive zeros are detected.
For long haul mode, loss is detected if the received signal level is 3dB lower from the programmed value (based on Table 10-18) for a duration of 192-bit periods. Hence, if the sensitivity is programmed at 30dB, loss declaration level will be 33dB. LOS is reset if all of the following criteria are met: * * 24 or more ones are detected in 192-bit period with a programmed sensitivity level measured at RTIP and RRING. During the 192 bits less than 100 consecutive zeros are detected.
9.11.3.6 ITU G.775 for E1 Modes
For short haul mode, loss is declared if the received signal level is 3dB lower from the programmed value (based on Table 10-18) for a duration of 192-bit periods. Hence, if the sensitivity is programmed to be 12dB, loss will be declared at 15dB. LOS is reset if the receive signal level is greater than or equal to the programmed sensitivity level for a duration of 192-bit periods. For long haul mode, loss is detected if the received signal level is 3dB lower from the programmed value (based on Table 10-18) for a duration of 192-bit periods. Hence, if the sensitivity is programmed at 30dB, loss declaration level will be 33dB. LOS is reset if the receive signal level is greater than or equal to the programmed sensitivity level for a duration of 192-bit periods.
9.11.3.7 ETSI 200 233 for E1 Modes
For short haul mode, loss is declared if the received signal level is 3dB lower from the programmed value (based on Table 10-18) continuous duration of 2048-bit periods (1ms). LOS is reset if the receive signal level is greater than or equal to programmed sensitivity level for a duration of 192-bit periods. For long haul mode, loss is declared if the received signal level is 3dB lower from the programmed value (based on Table 10-18) continuous duration of 2048 bit periods (1ms). LOS is reset if the receive signal level is greater than or equal to the programmed sensitivity level for a duration of 192-bit periods.
9.11.4 Jitter Attenuator
The DS26528 contains a jitter attenuator that can be set to a depth of 32 or 128-bits via the JADS bit in LIU Transmit and Receive Control Register (LTRCR). The 128-bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used in delay sensitive applications. The characteristics of the attenuation are shown in Figure 9-31. The jitter attenuator can be placed in either the receive path, the transmit path or disabled by appropriately setting the JAPS1 and JAPS0 bits in LIU Transmit and Receive Control Register (LTRCR). For the jitter attenuator to operate properly, a 2.048MHz, 1.544MHz, or a multiple of up to 8x clock must be applied at MCLK. See the Global Transceiver Clock Control Register (GTCCR ) for MCLK options. ITU specification G.703 requires an accuracy of 50ppm for both T1/J1 and E1 applications. TR62411 and ANSI specs require an accuracy of 32ppm for T1/J1 interfaces. Circuitry adjusts either the recovered clock from the clock/data recovery block or the clock applied at the TCLK pin to create a smooth jitter-free clock, which is used to clock data out of the jitter attenuator FIFO. It is acceptable to provide a gapped/bursty clock at the TCLK pin if the jitter attenuator is placed in 81 of 269
DS26528 Octal T1/E1/J1 Transceiver the transmit side. If the incoming jitter exceeds either 120UIP-P (buffer depth is 128-bits) or 28UIP-P (buffer depth is 32 bits), then the DS26528 will set the jitter attenuator limit trip (JALTS) bit in the LIU latched status register (LLSR). In T1/J1 mode, the jitter attenuator corner frequency is 3.75Hz and in E1 Mode it is 0.6Hz. The DS26528 jitter attenuator is complaint with the following specifications:
Table 9-36. Jitter Attenuator Standards Compliance
Standard ITUT I.431, G.703, G.736, G.823, ETSI 300011, TBR 12/12 AT&T TR62411, TR43802 TR-TSY 009, TR-TSY 253, TR-TSY 499
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Figure 9-31. Jitter Attenuation
0dB
TBR12 Prohibited Area ITU G.7XX Prohibited Area
JITTER ATTENUATION (dB)
-20dB
Cu e rv A
E1
T1
-40dB
B rve Cu
TR 62411 (Dec. 90) Prohibited Area
-60dB 1 10 100 1K FREQUENCY (Hz) 10K 100K
9.11.5 LIU Loopbacks
The DS26528 provides four LIU loopbacks for diagnostic purposes: analog loopback, local loopback, remote loopback and dual loopback. In the "loopback diagrams" that follow, the TSER, TCLK and RSER and RCLK are inputs/outputs from the framer. Note that the framer input/output can be in IBO mode where a single TSER/RSER can be shared by up to eight framers.
9.11.5.1
Analog Loopback
The analog output of the transmitter TTIP and TRING is looped back to RTIP and RRING of the receiver. Data at RTIP and RRING is ignored in analog loopback. This is shown in the following figure.
Figure 9-33. Analog Loopback
TCLK TSER
Optional Jitter Attenuator
Transmit Framer
Transmit Digital
Transmit Analog
Line Driver
RCLK
RSER
Receive Framer
Optional Jitter Attenuator
Receive Digital
Receive Analog
Rtip Rring
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9.11.5.2 Local Loopback
The transmit system data from the transmit framer will be looped back to the inputs of the receive framer. The data input to the transmit LIU will be encoded and output on TTIP and TRING. Signals at RTIP and RRING will be ignored. This loopback is conceptually shown in following figure.
Figure 9-35. Local Loopback
TCLK TSER
Transmit Framer
Optional Jitter Attenuator
Transmit Digital Transmit Analog
TPOS
Line Driver
TNEG
RCLK RSER
Receive Framer
Optional Jitter Attenuator
Receive Digital
RTIP
Receive Analog
RRING
9.11.5.3
Remote Loopback
The outputs decoded from the receive LIU are looped back to the transmit LIU. The inputs from the transmit framer are ignored during a remote loopback. This loopback is conceptually shown in Figure 9-37.
Figure 9-37. Remote Loopback
TCLK TSER
Transmit Framer
Optional Jitter Attenuator
Transmit Digital Transmit Analog
TPOS
Line Driver
TNEG
RCLK RSER
Receive Framer
Optional Jitter Attenuator
Receive Digital Receive Analog
RTIP RRING
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9.11.5.4 Dual Loopback
The inputs decoded from the receive LIU are looped back to the transmit LIU. The inputs from the transmit framer are looped back to the receiver with the optional jitter attenuator. This loopback is invoked if RLB and LLB are both set in the LIU Maintenance Control Register (LMCR). This loopback is conceptually shown in Figure 9-39.
Figure 9-39. Dual Loopback
TCLK TSER
Transmit Framer
Optional Jitter Attenuator
Transmit Digital Transmit Analog
TPOS
Line Driver
TNEG
RCLK RSER
Receive Framer
Optional Jitter Attenuator
Receive Digital Receive Analog
RTIP RRING
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9.12 Bit Error Rate Test Function (BERT)
The BERT (Bit Error Rate Tester) block can generate and detect both pseudo-random and repeating-bit patterns. It is used to test and stress data-communication links. BERT functionality is dedicated for each of the Transceivers. The registers related to the configure, control and status of the BERT are shown in the following table: REGISTER GBISR GBIMR RXPC RBPBS RBPCS1-4 TXPC TBPBS TBPCS1-4 BAWC BRP1 BRP2 BRP3 BRP4 BC1 BC2 BBC1 BBC2 BBC3 BBC4 BEC1 BEC2 BEC3 BLSR BSIM FRAMER 1 ADDRESSES 0FA 0FD 8A 8B D4, D5, D6, D7 18A 18B 1D4, 1D5, 1D6, 1D7 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 110A 110B 110C 110D 110E 110F FUNCTION Global BERT Interrupt Register. When any of the 8 BERTs issue an interrupt, a bit will be set. Global BERT Interrupt Mask Register. When any of the 8 BERTs issue an interrupt, a bit will be set. Enable for the Receiver BERT Bit Suppression for the Receive BERT Channels to be enabled for the Framer to accept data from the BERT pattern generator Enable for the Transmitter BERT Bit Suppression for the Transmit BERT Channels to be enabled for the Framer to accept data from the Transmit BERT pattern generator BERT Alternating Pattern Count Register BERT Repetitive Pattern Set Register 1 BERT Repetitive Pattern Set Register 2 BERT Repetitive Pattern Set Register 3 BERT Repetitive Pattern Set Register 4 Pattern Selection and Misc Control BERT Bit Pattern Length Control BERT Bit Counter--Increments for BERT Bit clocks BERT Bit Counter BERT Bit Counter BERT Bit Counter BERT Error Counter BERT Error Counter BERT Error Counter BERT Status Registers--Denotes Synchronization Loss and Other Status BERT Interrupt Mask
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 - 8 can be calculated using the following: Framer N = (Framer 1 address + (n-1) x 200hex); where n = 2 to 8 for Framers 2 to 8.
The BERT block can generate and detect the following patterns: * * * * The pseudo-random patterns 2E7-1, 2E9-1, 2E11-1, 2E15-1, and QRSS A repetitive pattern from 1 to 32 bits in length Alternating (16-bit) words that flip every 1 to 256 words Daly pattern
The BERT function must be enabled and configured in the TXPC and RXPC registers for each port. The BERT can then be assigned on a per-channel basis for both the transmitter and receiver, using the special per-channel function in the TBPCS1-4 and RBCS1-4 registers. Individual bit positions within the channels can be suppressed with the TBPBS and RBPBS registers. Using combinations of these functions, the BERT pattern can be transmitted and/or received in single or across multiple DS0s, contiguous or broken. Transmit and receive bandwidth assignments are independent of each other. The BERT receiver has a 32-bit bit counter and a 24-bit error counter. The BERT receiver can generate interrupts on: a change in receive-synchronizer status, receive all zeros, receive all ones, error counter overflow, bit counter 86 of 269
DS26528 Octal T1/E1/J1 Transceiver overflow, and bit error detection. Interrupts from each of these events can be masked within the BERT function via the BERT Status Interrupt Mask Register (BSIM). If the software detects that the BERT has reported an event, then the software must read the BERT Latched Status Register (BLSR) to determine which event(s) has occurred.
9.12.1 BERT Repetitive Pattern Set
These registers must be properly loaded for the BERT to generate and synchronize to a repetitive pattern, a pseudo-random pattern, alternating word pattern, or a Daly pattern. For a repetitive pattern that is less than 32 bits, the pattern should be repeated so that all 32 bits are used to describe the pattern. For example, if the pattern was the repeating 5-bit pattern ...01101... (where the right-most bit is the one sent first and received first) then BRP1 should be loaded with ADh, BRP2 with B5h, BRP3 with D6h, and BRP4 should be loaded with 5Ah. For a pseudorandom pattern, all four registers should be loaded with all ones (i.e., FFh). For an alternating word pattern, one word should be placed into BRP1 and BRP2 and the other word should be placed into BRP3 and BRP4. For example, if the DDS stress pattern "7E" is to be described, the user would place 00h in BRP1, 00h in BRP2, 7Eh in BRP3, and 7Eh in BRP4, and the alternating word counter would be set to 50 (decimal) to allow 100 bytes of 00h followed by 100 bytes of 7Eh to be sent and received.
9.12.2 BERT Error Counter
Once BERT has achieved synchronization, this 24-bit counter will increment for each data bit received in error. Toggling the LC control bit in BC1 can clear this counter. This counter saturates when full and will set the BECO status bit in the BLSR register.
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10.
DEVICE REGISTERS
Thirteen address bits are used to control the settings of the registers. The address map is compatible with the Maxim/Dallas Semiconductor octal framer product, DS26401. The registers control functions of the framers, LIUs, and BERTs within the DS26528. The map is divided into eight framers, followed by eight LIUs and eight BERTs. Global Registers (applicable to all eight transceivers and BERTs) are located within the address space of Framer 1. The Bulk Write Mode is a special mode to write all eight transceivers with one write command (see the GTCR1 register). Figure 10-1 shows the register map. The register details are provided in the following tables. The framer registers bits are provided for Framer 0 and address bits A11 to A8 determine the framer addressed.
10.1 Register Listings
The Framer Registers have an offset of 200 Hex, the LIU Registers have an offset of 20 Hex, and the BERT Registers have an offset of 10 Hex for each transceiver.
Table 10-1. Register Address Ranges (in Hex)
GLOBAL REGISTERS 00F0 - 00FF CH1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7 CH 8 -- -- -- -- -- -- -- -- RECEIVE FRAMER -- 0000 - 00EF 0200 - 02EF 0400 - 04EF 0600 - 06EF 0800 - 08EF 0A00 - 0AEF 0C00 - 0CEF 0E00 - 0EEF TRANSMIT FRAMER -- 0100 - 01EF 0300 - 03EF 0500 - 05EF 0700 - 07EF 0900 - 09EF 0B00 - 0BEF 0D00 - 0DEF 0F00 - 0FEF LIU -- 1000 - 101F 1020 - 103F 1040 - 105F 1060 - 107F 1080 - 109F 10A0 - 10BF 10C0 - 10DF 10E0 - 10FF BERT -- 1100 - 110F 1110 - 111F 1120 - 112F 1130 - 113F 1140 - 114F 1150 - 115F 1160 - 116F 1170 - 117F
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Figure 10-1. Register Memory Map for the DS26528
Adrs = 0000 0000 0000 Adrs = 0000 1111 0000 Adrs = 0001 0000 0000 Adrs = 0001 1111 0000 Adrs = 0010 0000 0000 Framer 2 Regs 3FF 400 Framer 3 Regs Framer 1 Rx Regs Global Registers Framer 1 Tx Regs Reserved 240 Regs 240 Regs 000
0EF 0F0 0FF 100 1EF 1F0 1FF
200
Adrs = 0100 0000 0000
Adrs = 0101 1111 1111 Adrs = 0110 0000 0000
5FF 600
Framer 4 Regs Adrs = 0111 1111 1111 Adrs = 1000 0000 0000 Framer 5 Regs Adrs = 01001 1111 1111 Adrs = 01010 0000 0000 Framer 6 Regs Adrs = 01011 1111 1111 Adrs = 01100 0000 0000 Framer 7 Regs BFF C00 9FF A00 7FF 800
Adrs = 01101 1111 1111 Adrs = 01110 0000 0000 Framer 8 Regs Adrs = 01111 1111 1111 Adrs = 10000 0000 0000 LIU Regs Adrs = 10000 1111 1111 Adrs = 10001 0000 0000 BERT Adrs = 10001 0111 1111 Reserved Adrs = 11111 1111 1111
DFF E00
FFF 1000 10FF 1100 117F
1FFF
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10.1.1 Global Register List
Table 10-2. Global Register List
GLOBAL REGISTER LIST ADDR 00F0 00F1 00F2 00F3 00F4 00F5 00F6 00F7 00F8 00F9 00FA 00FB 00FC 00FD 00FE 001F ABBR GTCR1 GFCR GTCR2 GTCCR GLSRR GFSRR IDR GFISR GBISR GLISR GFIMR GBIMR GLIMR DESCRIPTION Global Transceiver Control Register 1 Global Framer Control Register Global Transceiver Control Register 2 Global Transceiver Clock Control Register Reserved Global LIU Software Reset Register Global Framer and BERT Software Reset Register Reserved Device ID Register Global Framers Interrupt Status Register Global BERT Interrupt Status Register Global LIU Interrupt Status Register Global Framers Interrupt Mask Register Global BERT Interrupt Mask Register Global LIU Interrupt Mask Register Reserved R/W R/W R/W R/W R/W R/W R/W R R R R RW RW RW -
Note 1: Reserved registers should only be written with all zeros. Note 2: The global registers are located in the framer 1 address space. The corresponding address space for the other seven framers is "Reserved," and should be initialized with all zeros for proper operation.
10.1.2 Framer Register List
Table 10-3. Framer Register List
Note that only Framer 1 Address is presented here. The same set of registers definitions applies for transceiver 2 to 8 in accordance with the DS26528 map offsets. Transceiver offset is (n-1) x 200 hex, where n designates the transceiver in question.
ADDRESS 000 - 00F 010 011 012 013 014 015 016 - 01F 020 021 022 023 024 025 026 027 028 029 02A 02B 02C
ABBR RHC RHBSE RDS0SEL RSIGC T1RCR2
E1RSAIMR
T1RBOCC RIDR1 RIDR2 RIDR3 RIDR4 RIDR5 RIDR6 RIDR7 RIDR8 RIDR9 RIDR10 RIDR11 RIDR12 RIDR13
FRAMER REGISTER LIST DESCRIPTION Reserved Rx HDLC Control Rx HDLC Bit Suppress Rx DS0 Monitor Select Rx Signaling Control Rx Control 2 (T1 Mode) Rx Sa Bit Interrupt Mask Register (E1 Mode) Rx BOC Control (T1 Mode Only) Reserved Rx Idle Definition 1 Rx Idle Definition 2 Rx Idle Definition 3 Rx Idle Definition 4 Rx Idle Definition 5 Rx Idle Definition 6 Rx Idle Definition 7 Rx Idle Definition 8 Rx Idle Definition 9 Rx Idle Definition 10 Rx Idle Definition 11 Rx Idle Definition 12 Rx Idle Definition 13 90 of 269
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
DS26528 Octal T1/E1/J1 Transceiver FRAMER REGISTER LIST DESCRIPTION Rx Idle Definition 14 Rx Idle Definition 15 Rx Idle Definition 16 Rx Idle Definition 17 Rx Idle Definition 18 Rx Idle Definition 19 Rx Idle Definition 20 Rx Idle Definition 21 Rx Idle Definition 22 Rx Idle Definition 23 Rx Idle Definition 24 Rx Sig All Ones Insertion 1 (T1 Mode) Rx Idle Definition 25 (E1 Mode) Rx Sig All Ones Insertion 2 (T1 Mode) Rx Idle Definition 26 (E1 Mode) Rx Sig All Ones Insertion 3 (T1 Mode) Rx Idle Definition 27 (E1 Mode) Rx Idle Definition 28 (E1 Mode) Rx Digital Milliwatt Enable 1 (T1 Mode) Rx Idle Definition 29 (E1 Mode) Rx Digital Milliwatt Enable 2 (T1 Mode) Rx Idle Definition 30 (E1 Mode) Rx Digital Milliwatt Enable 3 (T1 Mode) Rx Idle Definition 31 (E1 Mode) Rx Idle Definition 32 (E1 Mode) Rx Signaling 1 Rx Signaling 2 Rx Signaling 3 Rx Signaling 4 Rx Signaling 5 Rx Signaling 6 Rx Signaling 7 Rx Signaling 8 Rx Signaling 9 Rx Signaling 10 Rx Signaling 11 Rx Signaling 12 Rx Signaling 13 (E1 Mode only) Rx Signaling 14 (E1 Mode only) Rx Signaling 15 (E1 Mode only) Rx Signaling 16 (E1 Mode only) Rx Line Code Violation Counter 1 Rx Line Code Violation Counter 2 Rx Path Code Violation Count 1 Rx Path Code Violation Count 2 Rx Frames Out of Sync Counter 1 Rx Frames Out of Sync Counter 2 E1 Receive E-Bit Counter 1 (E1 Mode Only) E1 Receive E-Bit Counter 2 (E1 Mode Only) Reserved Rx DS0 Monitor Reserved Rx FDL (T1 Mode) E1 Receive Real-Time Status 7 (E1 Mode) 91 of 269
ADDRESS 02D 02E 02F 030 031 032 033 034 035 036 037 038 039 03A 03B 03C 03D 03E 03F 040 041 042 043 044 045 046 047 048 049 04A 04B 04C 04D 04E 04F 050 051 052 053 054 055 056 057 058-05F 060 061 062
ABBR RIDR14 RIDR15 RIDR16 RIDR17 RIDR18 RIDR19 RIDR20 RIDR21 RIDR22 RIDR23 RIDR24 T1RSAOI1 E1RIDR25 T1RSAOI2 E1RIDR26 T1RSAOI3 E1RIDR27 E1RIDR28 T1RDMWE1 E1RIDR29 T1RDMWE2 E1RIDR30 T1RDMWE3 E1RIDR31 E1RIDR32 RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12 RS13 RS14 RS15 RS16 LCVCR1 LCVCR2 PCVCR1 PCVCR2 FOSCR1 FOSCR2 E1EBCR1 E1EBCR2 RDS0M T1RFDL E1RRTS7
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R R R R R R R R R R R R R R
DS26528 Octal T1/E1/J1 Transceiver FRAMER REGISTER LIST DESCRIPTION Rx BOC (T1 Mode Only) Rx SLC96 Data Link 1 (T1 Mode) E1 Receive Align Frame (E1 Mode) Rx SLC96 Data Link 2 (T1 Mode) E1 Receive Non-Align Frame (E1 Mode) Rx SLC96 Data Link 3 (T1 Mode) E1 Receive Si Bits for Align Frame (E1 Mode) E1 Receive Si Bits for Non-Align Frame (E1 Mode Only) E1 Receive Remote Alarm Bits (E1 Mode Only E1 Receive Sa4 Bits (E1 Mode Only) E1 Receive Sa5 Bits (E1 Mode Only) E1 Receive Sa6 Bits (E1 Mode Only) E1 Receive Sa7 Bits (E1 Mode Only) E1 Receive Sa8 Bits (E1 Mode Only) E1 Receive Sa Bits E1 Sa6 Codeword Reserved Rx Master Mode Rx Control 1 Rx In-Band Code Control (T1 Mode) E1 Rx Control 2 (E1 Mode) Rx Control 3 Rx I/O Configuration Rx Elastic Store Control Rx Error Count Configuration Rx HDLC FIFO Control Rx Interleave Bus Op Control Rx Spare Code Control (T1 Mode Only) Rx eXpansion Port Control Register Rx BERT Port Bit Suppress Register Reserved Rx Latched Status 1 Rx Latched Status 2 Rx Latched Status 3 Rx Latched Status 4 Rx Latched Status 5 Reserved Rx Latched Status 7 Reserved Rx Signaling CoS Status 1 Rx Signaling CoS Status 2 Rx Signaling CoS Status 3 Rx Signaling CoS Status 4 (E1 Mode Only) Rx Spare Code Definition 1 (T1 Mode Only) Rx Spare Code Definition 2 (T1 Mode Only) Reserved Rx Interrupt Information Reg Rx Interrupt Mask Reg 1 E1 Rx Interrupt Mask Reg 2 (E1 Mode Only) Rx Interrupt Mask Reg 3 Rx Interrupt Mask Reg 4 Rx Interrupt Mask Reg 5 Reserved Rx Interrupt Mask Reg 7 92 of 269
ADDRESS 063 064 065 066 067 068 069 06A 06B 06C 06D 06E 06F 070-07F 080 081 082 083 084 085 086 087 088 089 08A 08B 08C-08F 090 091 092 093 094 095 096 097 098 099 09A 09B 09C 09D 09E 09F 0A0 0A1 0A2 0A3 0A4 0A5 0A6
ABBR T1RBOC T1RSLC1 E1RAF T1RSLC2 E1RNAF T1RSLC3 E1RsiAF E1RSiNAF E1RNAF E1RSa4 E1RSa5 E1RSa6 E1RSa7 E1RSa8
SABITS Sa6CODE
R/W R R R R R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
RMMR RCR1 T1RIBCC E1RCR2 RCR3 RIOCR RESCR ERCNT RHFC RIBOC T1RSCC RXPC RBPBS RLS1 RLS2 RLS3 RLS4 RLS5 RLS7 RSS1 RSS2 RSS3 RSS4 T1RSCD1 T1RSCD2 RIIR RIM1 RIM2 RIM3 RIM4 RIM5 RIM7
DS26528 Octal T1/E1/J1 Transceiver FRAMER REGISTER LIST DESCRIPTION Reserved Rx Sig CoS Interrupt Enable 1 Rx Sig CoS Interrupt Enable 2 Rx Sig CoS Interrupt Enable 3 Rx Sig CoS Interrupt Enable 4 Rx Up Code Definition 1 (T1 Mode Only) Rx Up Code Definition 2 (T1 Mode Only) Rx Down Code Definition 1 (T1 Mode Only) Rx Down Code Definition 2 (T1 Mode Only) Rx Real-Time Status 1 Reserved Rx Real-Time Status 3 Reserved Rx Real-Time Status 5 (HDLC) Rx HDLC Packet Bytes Available Rx HDLC FIFO Reserved Rx Blank Channel Select 1 Rx Blank Channel Select 2 Rx Blank Channel Select 3 Rx Blank Channel Select 4 (E1 Mode Only) Rx Channel Blocking 1 Rx Channel Blocking 2 Rx Channel Blocking 3 Rx Channel Blocking 4 (E1 Mode Only) Rx Signaling Insertion 1 Rx Signaling Insertion 2 Rx Signaling Insertion 3 Rx Signaling Insertion 4 (E1 Mode Only) Rx Gapped Clock Channel Select 1 Rx Gapped Clock Channel Select 2 Rx Gapped Clock Channel Select 3 Rx Gapped Clock Channel Select 4 (E1 Mode Only) Rx Channel Idle Code Enable 1 Rx Channel Idle Code Enable 2 Rx Channel Idle Code Enable 3 Rx Channel Idle Code Enable 4 (E1 Mode Only) Rx BERT Port Channel Select Register 1 Rx BERT Port Channel Select Register 2 Rx BERT Port Channel Select Register 3 Rx BERT Port Channel Select Register 4 (E1 Mode Only) Reserved See the Global Register list in Table 10-2. Note that this space is "Reserved" in Framers 2-8. Reserved Tx HDLC Control 1 Tx HDLC Bit Suppress Reserved Tx HDLC Control 2 E1 Tx Sa Bit Control Register Reserved Tx Software Signaling Insertion Enable 1 Tx Software Signaling Insertion Enable 2 Tx Software Signaling Insertion Enable 3 93 of 269
ADDRESS 0A7 0A8 0A9 0AA 0AB 0AC 0AD 0AE 0AF 0B0 0B1 0B2 0B3 0B4 0B5 0B6 0B7-0BF 0C0 0C1 0C2 0C3 0C4 0C5 0C6 0C7 0C8 0C9 0CA 0CB 0CC 0CD 0CE 0CF 0D0 0D1 0D2 0D3 0D4 0D5 0D6 0D7 0D8-0EF 0F0-0FF 100-10F 110 111 112 113 114 115-117 118 119 11A
ABBR RSCSE1 RSCSE2 RSCSE3 RSCSE4 T1RUPCD1 T1RUPCD2 T1RDNCD1 T1RDNCD2 RRTS1 RRTS3 RRTS5 RHPBA RHF RBCS1 RBCS2 RBCS3 RBCS4 RCBR1 RCBR2 RCBR3 RCBR4 RSI1 RSI2 RSI3 RSI4 RGCCS1 RGCCS2 RGCCS3 RGCCS4 RCICE1 RCICE2 RCICE3 RCICE4 RBPCS1 RBPCS2 RBPCS3 RBPCS4 Global Registers (Section 10.3) THC1 THBSE THC2 E1TSACR SSIE1 SSIE2 SSIE3
R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
DS26528 Octal T1/E1/J1 Transceiver FRAMER REGISTER LIST DESCRIPTION Tx Software Signaling Insertion Enable 4 (E1 Mode Only) Reserved Tx Idle Definition 1 Tx Idle Definition 2 Tx Idle Definition 3 Tx Idle Definition 4 Tx Idle Definition 5 Tx Idle Definition 6 Tx Idle Definition 7 Tx Idle Definition 8 Tx Idle Definition 9 Tx Idle Definition 10 Tx Idle Definition 11 Tx Idle Definition 12 Tx Idle Definition 13 Tx Idle Definition 14 Tx Idle Definition 15 Tx Idle Definition 16 Tx Idle Definition 17 Tx Idle Definition 18 Tx Idle Definition 19 Tx Idle Definition 20 Tx Idle Definition 21 Tx Idle Definition 22 Tx Idle Definition 23 Tx Idle Definition 24 Tx Idle Definition 25 (E1 Mode Only) Tx Idle Definition 26 (E1 Mode Only) Tx Idle Definition 27 (E1 Mode Only) Tx Idle Definition 28 (E1 Mode Only) Tx Idle Definition 29 (E1 Mode Only) Tx Idle Definition 30 (E1 Mode Only) Tx Idle Definition 31 (E1 Mode Only) Tx Idle Definition 32 (E1 Mode Only) Tx Signaling 1 Tx Signaling 2 Tx Signaling 3 Tx Signaling 4 Tx Signaling 5 Tx Signaling 6 Tx Signaling 7 Tx Signaling 8 Tx Signaling 9 Tx Signaling 10 Tx Signaling 11 Tx Signaling 12 Tx Signaling 13 Tx Signaling 14 Tx Signaling 15 Tx Signaling 16 Tx Channel Idle Code Enable 1 Tx Channel Idle Code Enable 2 Tx Channel Idle Code Enable 3 Tx Channel Idle Code Enable 4 (E1 Mode Only) 94 of 269
ADDRESS 11B 11C-11F 120 121 122 123 124 125 126 127 128 129 12A 12B 12C 12D 12E 12F 130 131 132 133 134 135 136 137 138 139 13A 13B 13C 13D 13E 13F 140 141 142 143 144 145 146 147 148 149 14A 14B 14C 14D 14E 14F 150 151 152 153
ABBR SSIE4 Reserved TIDR1 TIDR2 TIDR3 TIDR4 TIDR5 TIDR6 TIDR7 TIDR8 TIDR9 TIDR10 TIDR11 TIDR12 TIDR13 TIDR14 TIDR15 TIDR16 TIDR17 TIDR18 TIDR19 TIDR20 TIDR21 TIDR22 TIDR23 TIDR24 TIDR25 TIDR26 TIDR27 TIDR28 TIDR29 TIDR30 TIDR31 TIDR32 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15 TS16 TCICE1 TCICE2 TCICE3 TCICE4
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
DS26528 Octal T1/E1/J1 Transceiver FRAMER REGISTER LIST DESCRIPTION Reserved Tx FDL (T1 Mode Only) Tx BOC (T1 Mode Only) Tx SLC96 Data Link 1 (T1 Mode) E1 Tx Align Frame (E1 Mode) Tx SLC96 Data Link 2 (T1 Mode) E1 Tx Non-Align Frame (E1 Mode) Tx SLC96 Data Link 3 (T1 Mode) E1 Tx Si bits for Align Frame (E1 Mode) E1 Tx Si bits for Non-Align Frame (E1 Mode Only) E1 Tx Remote Alarm (E1 Mode Only) E1 Tx Sa4 Bits (E1 Mode Only) E1 Tx Sa5 Bits (E1 Mode Only) E1 Tx Sa6 Bits (E1 Mode Only) E1 Tx Sa7 Bits (E1 Mode Only) E1 Tx Sa8 Bits (E1 Mode Only) Reserved Tx Master Mode Tx Control 1 Tx Control 2 Tx Control 3 Tx I/O Configuration Tx Elastic Store Control Tx Control 4 (T1 Mode Only) Tx HDLC FIFO Control Tx Interleave Bus Op Control Tx DS0 Monitor Select Tx eXpansion Port Control Tx BERT Port Bit Suppress Reserved Tx Synchronizer Control Reserved Tx Latched Status 1 Tx Latched Status 2 (HDLC) Tx Latched Status 3 (SYNC) Reserved Tx Interrupt Information Register Tx Interrupt Mask Register 1 Tx Interrupt Mask Register 2 (HDLC) Tx Interrupt Mask Register 3 (SYNC) Reserved Tx Code Definition 1 (T1 Mode Only) Tx Code Definition 2 (T1 Mode Only) Reserved Tx Real-Time Status Register 2 (HDLC) Reserved Tx HDLC FIFO Buffer Available Tx HDLC FIFO Reserved Tx DS0 Monitor Reserved Tx Blank Channel Select 1 Tx Blank Channel Select 2 Tx Blank Channel Select 3 95 of 269
ADDRESS 154-161 162 163 164 165 166 167 168 169 16A 16B 16C 16D 16E-17F 180 181 182 183 184 185 186 187 188 189 18A 18B 18C-18D 18E 18F 190 191 192 193-19E 19F 1A0 1A1 1A2 1A3-1AB 1AC 1AD 1AE-1B0 1B1 1B2 1B3 1B4 1B5-1BA 1BB 1BC-1BF 1C0 1C1 1C2
ABBR T1TFDL T1TBOC T1TSLC1 E1TAF T1TSLC2 E1TNAF T1TSLC3 E1TSiAF E1TSiNAF E1TRA E1TSa4 E1TSa5 E1TSa6 E1TSa7 E1TSa8 TMMR TCR1 TCR2 TCR3 TIOCR TESCR TCR4 THFC TIBOC TDS0SEL TXPC TBPBS TSYNCC Reserved TLS1 TLS2 TLS3 TIIR TIM1 TIM2 TIM3 T1TCD1 T1TCD2 TRTS2 TFBA THF TDS0M TBCS1 TBCS2 TBCS3
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R W R R/W R/W R/W
DS26528 Octal T1/E1/J1 Transceiver FRAMER REGISTER LIST DESCRIPTION Tx Blank Channel Select 4 (E1 Mode Only) Tx Channel Blocking 1 Tx Channel Blocking 2 Tx Channel Blocking 3 Tx Channel Blocking 4 (E1 Mode Only) Tx Hardware Signaling Channel Select 1 Tx Hardware Signaling Channel Select 2 Tx Hardware Signaling Channel Select 3 Tx Hardware Signaling Channel Select 4 (E1 Mode Only) Tx Gapped Clock Channel Select 1 Tx Gapped Clock Channel Select 2 Tx Gapped Clock Channel Select 3 Tx Gapped Clock Channel Select 4 (E1 Mode Only) Per-Channel Loopback Enable 1 Per-Channel Loopback Enable 2 Per-Channel Loopback Enable 3 Per-Channel Loopback Enable 4 (E1 Mode Only) Tx BERT Channel Select 1 Tx BERT Channel Select 2 Tx BERT Channel Select 3 Tx BERT Channel Select 4 (E1 Mode Only) Reserved
ADDRESS 1C3 1C4 1C5 1C6 1C7 1C8 1C9 1CA 1CB 1CC 1CD 1CE 1CF 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8-1FF
ABBR TBCS4 TCBR1 TCBR2 TCBR3 TCBR4 THSCS1 THSCS2 THSCS3 THSCS4 TGCCS1 TGCCS2 TGCCS3 TGCCS4 PCL1 PCL2 PCL3 PCL4 TBPCS1 TBPCS2 TBPCS3 TBPCS4 -
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -
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10.1.3 LIU and BERT Register List
Table 10-4. LIU Register List
ADDRESS 1000 1001 1002 1003 1004 1005 1006 1007 1008-101F LIU REGISTER LIST DESCRIPTION LIU Transmit Receive Control Register LIU Transmit Impedance Selection Register LIU Maintenance and Jitter Attenuator Control Register LIU Real Status Register LIU Status Interrupt Mask Register LIU Latched Status Register LIU Receive Signal Level LIU Receive Impedance and Sensitivity Monitor Register Reserved ABBR LTRCR LTISR LMJCR LRSR LSIMR LLSR LRSL LRISMR
Table 10-5. BERT Register List
ADDRESS 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 110A 110B 110C 110D 110E 110F BERT REGISTER LIST DESCRIPTION BERT Alternating Word Count Rate BERT Repetitive Pattern Set Register 1 BERT Repetitive Pattern Set Register 2 BERT Repetitive Pattern Set Register 3 BERT Repetitive Pattern Set Register 4 BERT Control Register 1 BERT Control Register 2 BERT Bit Count Register 1 BERT Bit Count Register 2 BERT Bit Count Register 3 BERT Bit Count Register 4 BERT Error Count Register 1 BERT Error Count Register 2 BERT Error Count Register 3 BERT Latched Status Register BERT Status Interrupt Mask Register ABBR BAWC BRP1 BRP2 BRP3 BRP4 BC1 BC2 BBC1 BBC2 BBC3 BBC4 BEC1 BEC2 BEC3 BLSR BSIMR
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10.2 Register Bit Maps
10.2.1 Global Register Bit Map
Table 10-6. Global Register Bit Map
ADDR 00F0 00F1 00F2 00F3 00F4 00F5 00F6 00F7 00F8 00F9 00FA 00FB 00FC 00FD 00FE NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 --RLOFLTS GIBO -BWE GCLE GTCR1 IBOMS1 IBOMS0 BPCLK1 BPCLK0 RFLOSSFS RFMSS TCBCS GFCR -----LOSS TSSYNIOSEL GTCR2 MPS1 GTCCR BPRFSEL3 BPRFSEL2 BPRFSEL1 BPRFSEL0 BFREQSEL FREQSEL GLSRR GFSRR IDR GFISR GBISR GLISR GFIMR GBIMR GLIMR
LSRST8 FSRST8 ID7 FIS8 BIS8 LSRST7 FSRST7 ID6 FIS7 BIS7 LSRST6 FSRST6 ID5 FIS6 BIS6 LSRST5 FSRST5 ID4 FIS5 BIS5 LSRST4 FSRST4 ID3 FIS4 BIS4 LSRST3 FSRST3 ID2 FIS3 BIS3 LSRST2 FSRST2 ID1 FIS2 BIS2
BIT 0
GIPI RCBCS -MPS0 LSRST1 FSRST1 ID0 FIS1 BIS1
LIS8 FIM8 BIM8 LIM8
LIS7 FIM7 BIM7 LIM7
LIS6 FIM6 BIM6 LIM6
LIS5 FIM5 BIM5 LIM5
LIS4 FIM4 BIM4 LIM4
LIS3 FIM3 BIM3 LIM3
LIS2 FIM2 BIM2 LIM2
LIS1 FIM1 BIM1 LIM1
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10.2.2 Framer Register Bit Map
Table 10-7 contains the framer registers of the DS26528. Some registers have dual functionality based on the selection of T1/J1 or E1 operating mode in the RMMR and TMMR registers. These dual-function registers are shown below using two lines of text. The first line of text is the bit functionality for T1/J1 mode. The second line is the bit functionality in E1 mode, in italics. Bits that are not used for an operating mode are noted with a single dash "-". When there is only one set of bit definitions listed for a register, the bit functionality does not change with respect to the selection of T1/J1 or E1 mode. All registers not listed are reserved and should be initialized with a value of 00h for proper operation. The addresses shown are for Framer 1. Addresses for Framers 2 - 8 can be calculated using the following formula: Address for Framer N = (Framer 1 address + (N-1) x 200hex).
Table 10-7. Framer Register Bit Map
ADDR 0010 0011 0012
0013 0014 0015 0020 0021 0022 0023 0024 0025 0026 0027 0028 0029 002A 002B 002C 002D 002E 002F 0030 0031 0032 0033 0034 0035 0036 0037 0038 0039 003A 003B 003C 003D 003E 003F
NAME RHC RHBSE RDS0SEL
RSIGC T1RCR2 E1RSAIMR T1RBOCC RIDR1 RIDR2 RIDR3 RIDR4 RIDR5 RIDR6 RIDR7 RIDR8 RIDR9 RIDR10 RIDR11 RIDR12 RIDR13 RIDR14 RIDR15 RIDR16 RIDR17 RIDR18 RIDR19 RIDR20 RIDR21 RIDR22 RIDR23 RIDR24 T1RSAOI1 RIDR25 T1RSAOI2 RIDR26 T1RSAOI3 RIDR27 RIDR28 T1RDMWE1 RIDR29 T1RDMWE2 RIDR30 T1RDMWE3 RIDR31 RIDR32
BIT 7 RCRCD BSE8 RBR C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 CH8 C7 CH16 C7 CH24 C7 C7 CH8 C7 CH16 C7 CH24 C7 -
BIT 6 RHR BSE7 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 CH7 C6 CH15 C6 CH23 C6 C6 CH7 C6 CH15 C6 CH23 C6 -
BIT 5 RHMS BSE6 RBD1 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 CH6 C5 CH14 C5 CH22 C5 C5 CH6 C5 CH14 C5 CH22 C5 -
BIT 4 RHCS4 BSE5 RCM4 RFSA1 CASMS RSLC96 Sa4IM RBD0 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 CH5 C4 CH13 C4 CH21 C4 C4 CH5 C4 CH13 C4 CH21 C4 -
BIT 3 RHCS3 BSE4 RCM3 OOF2 Sa5IM C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 CH4 C3 CH12 C3 CH20 C3 C3 CH4 C3 CH12 C3 CH20 C3 -
BIT 2 RHCS2 BSE3 RCM2 RSFF RSFF OOF1 Sa6IM RBF1 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 CH3 C2 CH11 C2 CH19 C2 C2 CH3 C2 CH11 C2 CH19 C2 -
BIT 1 RHCS1 BSE2 RCM1 RSFE RSFE RAIIE Sa7IM RBF0 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 CH2 C1 CH10 C1 CH18 C1 C1 CH2 C1 CH10 C1 CH18 C1 -
BIT 0 RHCS0 BSE1 RCM0 RSIE RSIE RD4RM Sa8IM C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 CH1 C0 CH9 C0 CH17 C0 C0 CH1 C0 CH9 C0 CH17 C0 -
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ADDR
0040 0041 0042 0043 0044 0045 0046 0047 0048 0049 004A 004B 004C 004D 004E 004F 0050 0051 0052 0053 0054 0055 0056 0057 0060 0061 0062 0063 0064 0065 0066 0067 0068 0069 006A 006B
NAME
RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12 RS13 RS14 RS15 RS16 LCVCR1 LCVCR2 PCVCR1 PCVCR2 FOSCR1 FOSCR2 E1EBCR1 E1EBCR2 RDS0M T1RFDL E1RRTS7 T1RBOC T1RSLC1 E1RAF T1RSLC2 E1RNAF T1RSLC3 E1RsiAF E1RSiNAF E1RNAF E1RSa4 E1RSa5 E1RSa6
BIT 7 C7 CH1-A 0 CH2-A CH1-A CH3-A CH2-A CH4-A CH3-A CH5-A CH4-A CH6-A CH5-A CH7-A CH6-A CH8-A CH7-A CH9-A CH8-A CH10-A CH9-A CH11-A CH10-A CH12-A CH11-A CH12-A CH13-A CH14-A CH15-A LCVC15 LCVC7 PCVC15 PCVC7 FOS15 FOS7 EB15 EB7 B1 RFDL7 CSC5 C8 Si M2 Si S=1 SiF14 SiF15 RRAF15 RSa4F15 RSa5F15 RSa6F15
BIT 6 C6 CH1-B 0 CH2-B CH1-B CH3-B CH2-B CH4-B CH3-B CH5-B CH4-B CH6-B CH5-B CH7-B CH6-B CH8-B CH7-B CH9-B CH8-B CH10-B CH9-B CH11-B CH10-B CH12-B CH11-B CH12-B CH13-B CH14-B CH15-B LCVC14 LCVC6 PCVC14 PCVC6 FOS14 FOS6 EB14 EB6 B2 RFDL6 CSC4 C7 0 M1 1 S4 SiF12 SiF13 RRAF13 RSa4F13 RSa5F13 RSa6F13
BIT 5 C5 CH1-C 0 CH2-C CH1-C CH3-C CH2-C CH4-C CH3-C CH5-C CH4-C CH6-C CH5-C CH7-C CH6-C CH8-C CH7-C CH9-C CH8-C CH10-C CH9-C CH11-C CH10-C CH12-C CH11-C CH12-C CH13-C CH14-C CH15-C LCVC13 LCVC5 PCVC13 PCVC5 FOS13 FOS5 EB13 EB5 B3 RFDL5 CSC3 RBOC5 C6 0 S=0 A S3 SiF10 SiF11 RRAF11 RSa4F11 RSa5F11 RSa6F11
BIT 4 C4 CH1-D 0 CH2-D CH1-D CH3-D CH2-D CH4-D CH3-D CH5-D CH4-D CH6-D CH5-D CH7-D CH6-D CH8-D CH7-D CH9-D CH8-D CH10-D CH9-D CH11-D CH10-D CH12-D CH11-D CH12-D CH13-D CH14-D CH15-D LCVC12 LCVC4 PCVC12 PCVC4 FOS12 FOS4 EB12 EB4 B4 RFDL4 CSC2 RBOC4 C5 1 S=1 Sa4 S2 SiF8 SiF9 RRAF9 RSa4F9 RSa5F9 RSa6F9
BIT 3 C3 CH13-A X CH14-A CH16-A CH15-A CH17-A CH16-A CH18-A CH17-A CH19-A CH18-A CH20-A CH19-A CH21-A CH20-A CH22-A CH21-A CH23-A CH22-A CH24-A CH23-A CH25-A CH24-A CH26-A CH27-A CH28-A CH29-A CH30-A LCVC11 LCVC3 PCVC11 PCVC3 FOS11 FOS3 EB11 EB3 B5 RFDL3 CSC0 RBOC3 C4 1 S=0 Sa5 S1 SiF6 SiF7 RRAF7 RSa4F7 RSa5F7 RSa6F7
BIT 2 C2 CH13-B Y CH14-B CH16-B CH15-B CH17-B CH16-B CH18-B CH17-B CH19-B CH18-B CH20-B CH19-B CH21-B CH20-B CH22-B CH21-B CH23-B CH22-B CH24-B CH23-B CH25-B CH24-B CH26-B CH27-B CH28-B CH29-B CH30-B LCVC10 LCVC2 PCVC10 PCVC2 FOS10 FOS2 EB10 EB2 B6 RFDL2 CRC4SA RBOC2 C3 0 C11 Sa6 A2 SiF4 SiF5 RRAF5 RSa4F5 RSa5F5 RSa6F5
BIT 1 C1 CH13-C X CH14-C CH16-C CH15-C CH17-C CH16-C CH18-C CH17-C CH19-C CH18-C CH20-C CH19-C CH21-C CH20-C CH22-C CH21-C CH23-C CH22-C CH24-C CH23-C CH25-C CH24-C CH26-C CH27-C CH28-C CH29-C CH30-C LCVC9 LCVC1 PCVC9 PCVC1 FOS9 FOS1 EB9 EB1 B7 RFDL1 CASSA RBOC1 C2 1 C10 Sa7 A1 SiF2 SiF3 RRAF3 RSa4F3 RSa5F3 RSa6F3
BIT 0 C0 CH13-D X CH14-D CH16-D CH15-D CH17-D CH16-D CH18-D CH17-D CH19-D CH18-D CH20-D CH19-D CH21-D CH20-D CH22-D CH21-D CH23-D CH22-D CH24-D CH23-D CH25-D CH24-D CH26-D CH27-D CH28-D CH29-D CH30-D LCCV8 LCVC0 PCVC8 PCVC0 FOS8 FOS0 EB8 EB0 B8 RFDL0 FASSA RBOC0 C1 1 C9 Sa8 M3 SiF0 SiF1 RRAF1 RSa4F1 RSa5F1 RSa6F1
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DS26528 Octal T1/E1/J1 Transceiver
ADDR
006C 006D 006E 006F 0080 0081 0082 0083 0084 0085 0086 0087 0088 0089 008A 008B 0090 0091 0092 0093 0094 0096 0097 0098 0099 009A 009B 009C 009D 009F 00A0 00A1 00A2 00A3 00A4 00A6 00A8 00A9 00AA 00AB 00AC
NAME
E1RSa7 E1RSa8 SABITS Sa6CODE RMMR RCR1 T1RIBCC E1RCR2 RCR3 RIOCR RESCR ERCNT RHFC RIBOC T1RSCC RXPC RBPBS RLS1 RLS2 RLS3 RLS4 RLS5 RLS7 RSS1 RSS2 RSS3 RSS4 T1RSCD1 T1RSCD2 RIIR RIM1 RIM2 RIM3 RIM4 RIM5 RIM7 RSCSE1 RSCSE2 RSCSE3 RSCSE4 T1RUPCD1
BIT 7 RSa7F15 RSa8F15 FRM_EN SYNCT RSa8S IDF RCLKINV RCLKINV RDATFMT 1SECS 1SECS RHPBMS BPBSE8 RRAIC RPDV LORCC LORCC RESF CH8 CH16 CH24 CH32 C7 C7 RRAIC LORCC LORCC RESF CH8 CH16 CH24 CH32 C7 -
BIT 6 RSa7F13 RSa8F13 INIT_DONE
RB8ZS RHDB3 RSa7S RSYNCINV RSYNCINV
RGCLKEN MCUS MCUS IBS1 RHPBEN BPBSE7 RAISC CRCRC LSPC RESEM CH7 CH15 CH23 CH31 C6 C6 RLS7 RAISC LSPC RESEM CH7 CH15 CH23 CH31 C6 -
BIT 5 BIT 4 BIT 3 BIT 2 RSa7F11 RSa7F9 RSa7F7 RSa7F5 RSa8F11 RSa8F9 RSa8F7 RSa8F5 Sa4 Sa5 Sa6 Sa6n Sa6n RFM ARC SYNCC RJC RSIGM RG802 RCRC4 FRC RUP2 RUP1 RUP0 RDN2 RSa6S RSa5S RSa4S RSERC H100EN RSCLKM RSMS RSIO H100EN RSCLKM RSIO RSZS RESALGN RESR MECU ECUS EAMS FSBE MECU ECUS EAMS IBS0 IBOSEL IBOEN DA2 RSC2 RHPAMS RHPAEN RBPDIR RBPDIR BPBSE6 BPBSE5 BPBSE4 BPBSE3 RLOSC RLOFC RRAID RAISD COFA 8ZD 16ZD SEFE CASRC FASRC RSA1 RSA0 LDNC LUPC LORCD LSPD V52LNKC RDMAC LORCD RSLIP RSCOS 1SEC ROVR RHOBT RPE RPS RRAI-CI RAIS-CI RSLC96 RFDLF CH6 CH5 CH4 CH3 CH14 CH13 CH12 CH11 CH22 CH21 CH20 CH19 CH30 CH29 CH28 CH27 C5 C4 C3 C2 C5 C4 C3 C2 RLS6** RLS5 RLS4 RLS3 RLS5 RLS4 RLS3 RLOSC RLOFC RRAID RAISD RSA1 RSA0 LDNC LUPC LORCD LSPD V52LNKC RDMAC LORCD RSLIP RSCOS 1SEC ROVR RHOBT RPE RPS RRAI-CI RAIS-CI RSLC96 RFDLF CH6 CH5 CH4 CH3 CH14 CH13 CH12 CH11 CH22 CH21 CH20 CH19 CH30 CH29 CH28 CH27 C5 C4 C3 C2 -
BIT 1 RSa7F3 RSa8F3 Sa7 Sa6n SFTRST SYNCE SYNCE RDN1 PLB RSMS2 RSMS2 RESMDM MOSCRF RFHWM1 DA1 RSC1 RBPFUS BPBSE2 RLOSD B8ZS RCMF LDND V52LNKD TIMER RHWMS BC Sa6CD CH2 CH10 CH18 CH26 C1 C1 RLS2* RLS2 RLOSD RCMF LDND V52LNKD TIMER RHWMS BC Sa6CD CH2 CH10 CH18 CH26 C1 -
BIT 0 RSa7F1 RSa8F1 Sa8 Sa6n T1/E1 RESYNC RESYNC RDN0 RLOSA FLB RSMS1 RSMS1 RESE LCVCRF LCVCRF RFHWM0 DA0 RSC0 RBPEN RBPEN BPBSE1 RLOFD FBE RAF LUPD RDMAD RMF RNES BD SaXCD CH1 CH9 CH17 CH25 C0 C0 RLS1 RLS1 RLOFD RAF LUPD RDMAD RMF RNES BD SaXCD CH1 CH9 CH17 CH25 C0 -
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DS26528 Octal T1/E1/J1 Transceiver
ADDR
00AD 00AE 00AF 00B0 00B2 00B4 00B5 00B6 0C00 00C1 00C2 00C3 00C4 00C5 00C6 00C7 00C8 00C9 00CA 00CB 00CC 00CD 00CE 00CF 00D0 00D1 00D2 00D3 00D4 00D5 00D6 00D7 0110 0111 0113 0118 0119 011A 011B 0120 0121 0122 0123 0124 0125 0126 0127 0128 0129
NAME
T1RUPCD2 T1RDNCD1 T1RDNCD2 RRTS1 RRTS3 RRTS5 RHPBA RHF RBCS1 RBCS2 RBCS3 RBCS4 RCBR1 RCBR2 RCBR3 RCBR4 RSI1 RSI2 RSI3 RSI4 RGCCS1 RGCCS2 RGCCS3 RGCCS4 RCICE1 RCICE2 RCICE3 RCICE4 RBPCS1 RBPCS2 RBPCS3 RBPCS4 THC1 THBSE THC2 SSIE1 SSIE2 SSIE3 SSIE4 TIDR1 TIDR2 TIDR3 TIDR4 TIDR5 TIDR6 TIDR7 TIDR8 TIDR9 TIDR10
BIT 7 C7 C7 C7 MS RHD7 CH8 CH16 CH24 CH32 CH8 CH16 CH24 CH32 CH8 CH16 CH24 CH32 CH8 CH16 CH24 CH32 CH8 CH16 CH24 CH32 CH8 CH16 CH24 CH32 NOFS TBSE8 TABT TABT CH8 CH16 CH24 CH32 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7
BIT 6 C6 C6 C6 PS2 RPBA6 RHD6 CH7 CH15 CH23 CH31 CH7 CH15 CH23 CH31 CH7 CH15 CH23 CH31 CH7 CH15 CH23 CH31 CH7 CH15 CH23 CH31 CH7 CH15 CH23 CH31 TEOML TBSE7 SBOC CH7 CH15 CH23 CH31 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6
BIT 5 C5 C5 C5 PS1 RPBA5 RHD5 CH6 CH14 CH22 CH30 CH6 CH14 CH22 CH30 CH6 CH14 CH22 CH30 CH6 CH14 CH22 CH30 CH6 CH14 CH22 CH30 CH6 CH14 CH22 CH30 THR TBSE6 THCEN THCEN CH6 CH14 CH22 CH30 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5
BIT 4 C4 C4 C4 PS0 RPBA4 RHD4 CH5 CH13 CH21 CH29 CH5 CH13 CH21 CH29 CH5 CH13 CH21 CH29 CH5 CH13 CH21 CH29 CH5 CH13 CH21 CH29 CH5 CH13 CH21 CH29 THMS TBSE5 THCS4 THCS4 CH5 CH13 CH21 CH29 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4
BIT 3 C3 C3 C3 RRAI LORC LORC RPBA3 RHD3 CH4 CH12 CH20 CH28 CH4 CH12 CH20 CH28 CH4 CH12 CH200 CH28 CH4 CH12 CH20 CH28 CH4 CH12 CH20 CH28 CH4 CH12 CH20 CH28 TFS TBSE4 THCS3 THCS3 CH4 CH12 CH20 CH28 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3
BIT 2 C2 C2 C2 RAIS LSP RPBA2 RHD2 CH3 CH11 CH19 CH27 CH3 CH11 CH19 CH27 CH3 CH11 CH19 CH27 CH3 CH11 CH19 CH27 CH3 CH11 CH19 CH27 CH3 CH11 CH19 CH27 TEOM TBSE3 THCS2 THCS2 CH3 CH11 CH19 CH27 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2
BIT 1 C1 C1 C1 RLOS LDN V52LNK RHWM RPBA1 RHD1 CH2 CH10 CH18 CH26 CH2 CH10 CH18 CH26 CH2 CH100 CH18 CH26 CH2 CH10 CH18 CH26 CH2 CH10 CH18 CH26 CH2 CH10 CH18 CH26 TZSD TBSE2 THCS1 THCS1 CH2 CH10 CH18 CH26 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1
BIT 0 C0 C0 C0 RLOF LUP RDMA RNE RPBA0 RHD0 CH1 CH9 CH17 CH25 CH1 CH9 CH17 CH25:Fbit CH1 CH9 CH17 CH25 CH1 CH9 CH17 CH25/Fbit CH1 CH9 CH17 CH25 CH1 CH9 CH17 CH25 TCRCD TBSE1 THCS0 THCS0 CH1 CH9 CH17 CH25 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0
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DS26528 Octal T1/E1/J1 Transceiver
ADDR 012A 012B 012C 012D 012E 012F 0130 0131 0132 0133 0134 0135 0136 0137
0138 0139 013A 013B 013C 013D 013E 013F 0140 0141 0142 0143 0144 0145 0146 0147 0148 0149 014A 014B 014C 014D 014E 014F
NAME TIDR11 TIDR12 TIDR13 TIDR14 TIDR15 TIDR16 TIDR17 TIDR18 TIDR19 TIDR20 TIDR21 TIDR22 TIDR23 TIDR24
TIDR25 TIDR26 TIDR27 TIDR28 TIDR29 TIDR30 TIDR31 TIDR32 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15 TS16
BIT 7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 C7 CH1-A 0 CH2-A CH1-A CH3-A CH2-A CH4-A CH3-A CH5-A CH4-A CH6-A CH5-A CH7-A CH6-A CH8-A CH7-A CH9-A CH8-A CH10-A CH9-A CH11-A CH10-A CH12-A CH11-A CH12-A CH13-A CH14-A CH15-A
BIT 6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 C6 CH1-B 0 CH2-B CH1-B CH3-B CH2-B CH4-B CH3-B CH5-B CH4-B CH6-B CH5-B CH7-B CH6-B CH8-B CH7-B CH9-B CH8-B CH10-B CH9-B CH11-B CH10-B CH12-B CH11-B CH12-B CH13-B CH14-B CH15-B
BIT 5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 C5 CH1-C 0 CH2-C CH1-C CH3-C CH2-C CH4-C CH3-C CH5-C CH4-C CH6-C CH5-C CH7-C CH6-C CH8-C CH7-C CH9-C CH8-C CH10-C CH9-C CH11-C CH10-C CH12-C CH11-C CH12-C CH13-C CH14-C CH15-C
BIT 4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 C4 CH1-D 0 CH2-D CH1-D CH3-D CH2-D CH4-D CH3-D CH5-D CH4-D CH6-D CH5-D CH7-D CH6-D CH8-D CH7-D CH9-D CH8-D CH10-D CH9-D CH11-D CH10-D CH12-D CH11-D CH12-D CH13-D CH14-D CH15-D
BIT 3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 C3 CH13-A X CH14-A CH16-A CH15-A CH17-A CH16-A CH18-A CH17-A CH19-A CH18-A CH20-A CH19-A CH21-A CH20-A CH22-A CH21-A CH23-A CH22-A CH24-A CH23-A CH25-A CH24-A CH26-A CH27-A CH28-A CH29-A CH30-A
BIT 2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 C2 CH13-B Y CH14-B CH16-B CH15-B CH17-B CH16-B CH18-B CH17-B CH19-B CH18-B CH20-B CH19-B CH21-B CH20-B CH22-B CH21-B CH23-B CH22-B CH24-B CH23-B CH25-B CH24-B CH26-B CH27-B CH28-B CH29-B CH30-B
BIT 1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 C1 CH13-C X CH14-C CH16-C CH15-C CH17-C CH16-C CH18-C CH17-C CH19-C CH18-C CH20-C CH19-C CH21-C CH20-C CH22-C CH21-C CH23-C CH22-C CH24-C CH23-C CH25-C CH24-C CH26-C CH27-C CH28-C CH29-C CH30-C
BIT 0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 CH13-D X CH14-D CH16-D CH15-D CH17-D CH16-D CH18-D CH17-D CH19-D CH18-D CH20-D CH19-D CH21-D CH20-D CH22-D CH21-D CH23-D CH22-D CH24-D CH23-D CH25-D CH24-D CH26-D CH27-D CH28-D CH29-D CH30-D
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DS26528 Octal T1/E1/J1 Transceiver
ADDR 0150 0151 0152
0153 0162 0163 0164 0165 0166 0167 0168 0169 016A 016B 016C 016D 0180 0181 0182 0183 0184 0185 0186 0187 0188 0189 018A 018B 018E 0190 0191 0192 019F 01A0 01A1 01A2 01AC
NAME TCICE1 TCICE2 TCICE3
TCICE4 T1TFDL T1TBOC T1TSLC1 E1TAF T1TSLC2 E1TNAF T1TSLC3 E1TSiAF E1TSiNAF E1TRA E1TSa4 E1TSa5 E1TSa6 E1TSa7 E1TSa8 TMMR TCR1 TCR2 TCR3 TIOCR TESCR TCR4 THFC TIBOC TDS0SEL TXPC TBPBS TSYNCC TLS1 TLS2 TLS3 TIIR TIM1 TIM2 TIM3 T1TCD1
BIT 7 CH8 CH16 CH24 CH32 CH8 C8 Si M2 Si S=1 TSiF14 TsiF15 TRAF15 TSa4F15 TSa5F15 TSa6F15 TSa7F15 TSa8F15 FRM_EN TJC TTPT TFDLS AEBE ODF ODF TCLKINV TCLKINV TDATFMT THPBMS BPBSE8 TESF TESF TESF TESF C7 -
BIT 5 CH6 CH14 CH22 CH30 CH6 TBOC5 C6 0 S=0 A S3 TSiF10 TSiF11 TRAF11 TSa4F11 TSa5F11 TSa6F11 TSa7F11 TSa8F11 INIT_DONE TFPT TCPT T16S TG802 TSLC96 AAIS ARA ODM TCSS1 ODM TCSS1
TSYNCINV TSSYNCINV TSYNCINV TSSYNCINV
BIT 6 CH7 CH15 CH23 CH31 CH7 C7 0 M1 1 S4 TSiF12 TSiF13 TRAF13 TSa4F13 TSa5F13 TSa6F13 TSa7F13 TSa8F13
TGCLKEN -IBS1 IBS0 THPBEN THPAMS BPBSE7 BPBSE6 TESEM TSLIP TESEM TSLIP TESEM TSLIP TESEM TSLIP C6 C5 -
BIT 4 BIT 3 BIT 2 CH5 CH4 CH3 CH13 CH12 CH11 CH21 CH20 CH19 CH29 CH28 CH27 CH5 CH4 CH3 TBOC4 TBOC3 TBOC2 C5 C4 C3 1 1 0 S=1 S=0 C11 Sa4 Sa5 Sa6 S2 S1 A2 TsiF8 TsiF6 TSiF4 TSiF9 TSiF7 TSiF5 TRAF9 TRAF7 TRAF5 TSa4F9 TSa4F7 TSa4F5 TSa5F9 TSa5F7 TSa5F5 TSa6F9 TSa6F7 TSa6F5 TSa7F9 TSa7F7 TSa7F5 TSa8F9 TSa8F7 TSa8F5 TSSE GB7S TB8ZS TSiS TSA1 THDB3 FBCT2 FBCT1 TD4RM Sa4S Sa5S Sa6S TCSS0 MFRS TFM TCSS0 MFRS TSCLKM TSSM TSIO TSCLKM TSSM TSIO TSZS TESALGN TESR TRAIM TAISM IBOSEL IBOEN DA2 TCM4 TCM3 TCM2 THPAEN TBPDIR BPBSE5 BPBSE4 BPBSE3 TSEN CRC4 TSEN TSLC96 TPDV TMF TAF TMF TFDLE TUDR TMEND TUDR TMEND TLS3 TSLC96 TPDV TMF TAF TMF TFDLE TUDR TMEND TUDR TMEND C4 C3 C2 -
BIT 1 BIT 0 CH2 CH1 CH10 CH9 CH18 CH17 CH26 CH25 CH2 CH1 TBOC1 TBOC0 C2 C1 1 1 C10 C9 Sa7 Sa8 A1 M3 TsiF2 TsiF0 TSiF3 TSiF1 TRAF3 TRAF1 TSa4F3 TSa4F1 TSa5F3 TSa5F1 TSa6F3 TSa6F1 TSa7F3 TSa7F1 TSa8F3 TSa8F1 SFTRST T1/E1 TAIS TRAI TAIS TCRC4 PDE TB7ZS Sa7S Sa8S IBPV TLOOP IBPV CRC4R TSDW TSM TSM TESMDM TESE TC1 TC0 TFLWM1 TFLWM2 DA1 DA0 TCM1 TCM0 TBPFUS TBPEN BPBSE2 BPBSE1 SYNCE RESYNC SYNCE RESYNC LOTCC LOTC LOTCC LOTC TLWMS TNFS TLWMS TNFS LOF LOFD TLS2 TLS1 LOTCC LOTC LOTCC LOTC TLWMS TNFS TLWMS TNFS LOFD C1 C0 -
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DS26528 Octal T1/E1/J1 Transceiver
ADDR
01AD 01B1 01B3 01B4 01BB 01C0 01C1 01C2 01C3 01C4 01C5 01C6 01C7 01C8 01C9 01CA 01CB 01CC 01CD 01CE 01CF 01D0 01D1 01D2 01D3 01D4 01D5 01D6 01D7
NAME
T1TCD2 TRTS2 TFBA THF TDS0M TBCS1 TBCS2 TBCS3 TBCS4 TCBR1 TCBR2 TCBR3 TCBR4 THSCS1 THSCS2 THSCS3 THSCS4 TGCCS1 TGCCS2 TGCCS3 TGCCS4 PCL1 PCL2 PCL3 PCL4 TBPCS1 TBPCS2 TBPCS3 TBPCS4
BIT 7 C7 -THD7 B1 CH8 CH16 CH24 CH32 CH8 CH16 CH24 CH32 CH8 CH16 CH24 CH32 CH8 CH16 CH24
CH32 CH8 CH16 CH24 CH32 CH8 CH16 CH24 CH32
BIT 6 C6 TFBA6 THD6 B2 CH7 CH15 CH23 CH31 CH7 CH15 CH23 CH31 CH7 CH15 CH23 CH31 CH7 CH15 CH23
CH31 CH7 CH15 CH23 CH31 CH7 CH15 CH23 CH31
BIT 5 C5 TFBA5 THD5 B3 CH6 CH14 CH22 CH30 CH6 CH14 CH22 CH30 CH6 CH14 CH22 CH30 CH6 CH14 CH22
CH30 CH6 CH14 CH22 CH30 CH6 CH14 CH22 CH30
BIT 4 C4 TFBA4 THD4 B4 CH5 CH13 CH21 CH29 CH5 CH13 CH21 CH29 CH5 CH13 CH21 CH29 CH5 CH13 CH21
CH29 CH5 CH13 CH21 CH29 CH5 CH13 CH21 CH29
BIT 3 C3 TEMPTY TFBA3 THD3 B5 CH4 CH12 CH20 CH28 CH4 CH12 CH20 CH28 CH4 CH12 CH20 CH28 CH4 CH12 CH20
CH28 CH4 CH12 CH20 CH28 CH4 CH12 CH20 CH28
BIT 2 C2 TFULL TFBA2 THD2 B6 CH3 CH11 CH19 CH27 CH3 CH11 CH19 CH27 CH3 CH11 CH19 CH27 CH3 CH11 CH19
CH27 CH3 CH11 CH19 CH27 CH3 CH11 CH19 CH27
BIT 1 C1 TLWM TFBA1 THD1 B7 CH2 CH10 CH18 CH26 CH2 CH10 CH18 CH26 CH2 CH10 CH18 CH26 CH2 CH10 CH18
CH26 CH2 CH10 CH18 CH26 CH2 CH10 CH18 CH26
BIT 0 C0 TNF TFBA0 THD0 B8 CH1 CH9 CH17 CH25 CH1 CH9 CH17 CH25:Fbit CH1 CH9 CH17 CH25 CH1 CH9 CH17 CH25: Fbit CH1 CH9 CH17 CH25 CH1 CH9 CH17 CH25
10.2.3 LIU Register Bit Map
Table 10-8. LIU Register Bit Map
ADDR 1000 1001 1002 1003 1004 1005 1006 1007 NAME BIT 7 BIT 6 BIT 5 LTRCR ---LTITSR -TIMPTOFF TIMPL1 LMCR TAIS ATAIS LLB LRSR --OEQ LSIMR JALTRSIM OCSRIM SCSRIM LLSR JFLTRLS OCRLS SCRLS LRSL RSL3 RSL2 RLS1 LRISMR RG703 RIMPOFF RIMPM1 BIT 4 JADS TIMPL0 ALB UEQ LOSRIM LOSRLS RLS0 RIMPM0 BIT 2 JAPS0 TS2 TPDE SCS JALTSSIM OCSSIM JALTSLS OCSLS --RTR RMONEN BIT 3 JAPS1 -RLB BIT 1 T1J1E1S TS1 RPDE OCS SCSSIM SCSLS -RSMS1 BIT 0 LSC TS0 TXEN LOSS LOSSIM LOSSLS -RSMS0
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DS26528 Octal T1/E1/J1 Transceiver
10.2.4 BERT Register Bit Map
Table 10-9. BERT Register Bit Map
ADDR NAME
1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 110A 110B 110C 110D 110E 110F
BAWC BRP1 BRP2 BRP3 BRP4 BC1 BC2 BBC1 BBC2 BBC3 BBC4 BEC1 BEC2 BEC3 BLSR BSIM
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ACNT7 ACNT6 ACNT5 ACNT4 ACNT3 ACNT2 ACNT1 ACNT0 RPAT7 RPAT6 RPAT5 RPAT4 RPAT3 RPAT2 RPAT1 RPAT0 RPAT15 RPAT14 RPAT13 RPAT12 RPAT11 RPAT10 RPAT9 RPAT8 RPAT23 RPAT22 RPAT21 RPAT20 RPAT19 RPAT18 RPAT17 RPAT16 RPAT31 RPAT30 RPAT29 RPAT28 RPAT27 RPAT26 RPAT25 RPAT24 TC TINV RINV PS2 PS1 PS0 LC RESYNC EIB2 EIB1 EIB0 SBE RPL3 RPL2 RPL1 RPL0 BBC7 BBC6 BBC5 BBC4 BBC3 BBC2 BBC1 BBC0 BBC15 BBC14 BBC13 BBC12 BBC11 BBC10 BBC9 BBC8 BBC23 BBC22 BBC21 BBC20 BBC19 BBC18 BBC17 BBC16 BBC31 BBC30 BBC29 BBC28 BBC27 BBC26 BBC25 BBC24 EC7 EC6 EC5 EC4 EC3 EC2 EC1 EC0 EC15 EC14 EC13 EC12 EC11 EC10 EC9 EC8 EC23 EC22 EC21 EC20 EC19 EC18 EC17 EC16 BBED BBCO BEC0 BRA1 BRA0 BRLOS BSYNC BBED BBCO BEC0 BRA1 BRA0 BRLOS BSYNC
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DS26528 Octal T1/E1/J1 Transceiver
10.3 Global Register Definitions
Functions contained in the global registers include: framer reset, LIU reset, device ID, BERT interrupt status, framer interrupt status, IBO configuration, MCLK configuration, and BPCLK configuration. The global registers bit descriptions are presented below.
Register Name Register Description: Register Address: Read/Write Function
GTCR1 Global Transceiver Control Register 1 0F0H R/W 6 -0 5 RLOFLTS 0 4 GIBO 0 3 -0 2 BWE 0 1 GCLE 0 0 GIPI 0
Bit # Name Default
7 -0
Bit 5 : Receive Loss Of Frame / Loss of Transmit Clock Indication Select (RLOFLTS). 0 = RLOF/LOTCx pins indicate framer receive loss of frame 1 = RLOF/LOTCx pins indicate framer loss of transmit clock Bit 4 : Ganged IBO Enable (GIBO). This bit is used to select either the internal mux for IBO operation or an external "wire-OR" operation. Normally this bit should be set = 0 and the internal mux used. 0 = Use internal IBO mux. 1 = Externally "wire-OR" TSERs and RSERs for IBO operation. Bits 2 : Bulk Write Enable (BWE). When this bit is set, a port write to one of the octal ports will be mapped into all eight ports. This applies to the framer, BERT and LIU register sets. It must be cleared before performing a read operation. This bit is useful for device initialization. 0 = Normal operation 1 = Bulk write is enabled Bit 1 : Global Counter Latch Enable (GCLE). A low-to-high transition on this bit will, when enabled, latch the framer performance monitor counters. Each framer can be independently enabled to accept this input. This bit must be cleared and set again to perform another counter latch. Bit 0 : Global Interrupt Pin Inhibit (GIPI). 0 = Normal Operation. Interrupt pin (INT) will toggle low on an un-masked interrupt condition 1 = Interrupt Inhibit. Interrupt pin (INT) is forced high (inactive) when this bit is set.
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Description: Register Address: Read/Write Function
GFCR Global Framer Control Register 0F1H R/W 6 IBOMS0 0 5 BPCLK1 0 4 BPCLK0 0 3 RFLOSSFS 0 2 RFMSS 0 1 TCBCS 0 0 RCBCS 0
Bit # Name Default
7 IBOMS1 0
Bits 7, 6 : Interleave Bus Operation Mode Select 1, 0 (IBOMS[1:0]). These bits determine the configuration of the IBO (interleaved bus) multiplexer. These bits should be used in conjunction with the Rx and Tx IBO control registers within each of the framer units. Additional information concerning the IBO multiplexer is given in Section 9.8.2. IBOMS1 0 0 1 1 IBOMS0 0 1 0 1 IBO Mode IBO Multiplexer Disabled 2 devices on bus (4.096MHz) 4 devices on bus (8.192MHz) 8 devices on bus (16.384MHz)
Bits 5, 4 : Backplane Clock Select 1, 0 (BPCLK[1:0]). These bits determine the clock frequency output on the BPCLK pin. BPCLK1 0 0 1 1 BPCLK0 0 1 0 1 BPCLK Frequency 2.048MHz 4.096MHz 8.192MHz 16.384MHz
Bit 3 : Receive Loss of Signal / Signaling Freeze Select (RLOSSFS). This bit controls the function of all eight AL/RSIGF/FLOS pins. The Receive LOS is further selected between Framer LOS and LIU LOS by GTCR2 Bit 2. 0 = AL/RSIGF/FLOS pins output RLOS (1-8) (Receive Loss) 1 = AL/RSIGF/FLOS pins output RSIGF (1-8) (Receive Signaling Freeze) Bit 2 : Receive Frame/Multiframe Sync Select (RFMSS). This bit controls the function of all eight RM/RFSYNC pins. 0 = RM/RFSYNC pins output RFSYNC (1-8) (Receive Frame Sync) 1 = RM/RFSYNC pins output RMSYNC (1-8) (Receive Multi-Frame Sync) Bit 1 : Transmit Channel Block/Clock Select (TCBCS). This bit controls the function of all eight TCHBLK/CLK pins. 0 = TCHBLK/CLK pins output TCHBLK (1-8) (Transmit Channel Block) 1 = TCHBLK/CLK pins output TCHCLK (1-8) (Transmit Channel Clock) Bit 0 : Receive Channel Block/Clock Select (RCBCS). This bit controls the function of all eight RCHBLK/CLK pins. 0 = RCHBLK/CLK pins output RCHBLK (1-8) (Receive Channel Block) 1 = RCHBLK/CLK pins output RCHCLK (1-8) (Receive Channel Clock)
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DS26528 Octal T1/E1/J1 Transceiver Register Name:
Register Description: Register Address: Read/Write Function
GTCR2 Global Transceiver Control Register 2 0F2H R/W 6 -0 5 -0 4 -0 3 -0 2 LOSS 0 1 TSSYNIOSEL 0 0 -0
Bit # Name Default
7 -0
Bit 2 : LOS Selection. If this bit is set, the AL/RSIGF/FLOS pins can be driven with LIU Loss and if reset by Framer LOS . The selection of whether to drive AL/RSIGF/FLOS pins with LOS(Analog or Digital) or Signalling Freeze is controlled by GFCR bit 2. This selection effects all ports Bit 1 : Transmit System Synchronization I/0 Select (TSSYNCIOSEL). If this bit is set to a 1 the TSSYNCIO is an 8kHz output synchronous to the BPCLK. This "frame pulse" can be used in conjunction with the Backplane clock to provide IBO signals for a System Backplane. If this bit is reset TSSYNCIO is an input. An 8kHz frame pulse is required for Transmit Synchronization and IBO operation
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DS26528 Octal T1/E1/J1 Transceiver Register Name:
Register Description: Register Address: Read/Write Function
GTCCR Global Transceiver Clock Control Register 0F3H R/W 6
BPREFSEL2
Bit # Name Default
7
BPREFSEL3
5
BPREFSEL1
4
BPREFSEL0
3
BFREQSEL
2
FREQSEL
1
MPS1
0
MPS0
0
0
0
0
0
0
0
0
Bits 7 to 4 : Backplane Clock Reference Selects (BPREFSEL[3:0]).These bits select which reference clock source will be used for BPCLK generation. The BPCLK can be generated from any of the LIU recovered clocks, an external reference or derivatives of MCLK input. This is shown in Table 10-10. See Figure 9-1 for additional information. Bit 3 : Backplane Frequency Select. In conjunction with BPRFSEL[3:0] identifies the reference clock frequency used by the DS26528 backplane clock generation circuit. Note that the setting of this bit should match the T1E1 selection for the LIU whose recovered clock is being used to generate the backplane clock. See Figure 9-1 for additional information. 0 = Backplane reference clock is 2.048MHz. 1 = Backplane reference clock is 1.544MHz. Bit 2 : Frequency Selection (FREQSEL). In conjunction with the MPS[1:0] bits, selects the external MCLK frequency of the signal input at the MCLK pin of the DS26528. 0 = The external master clock is 2.048MHz or multiple thereof. 1 = The external master clock is 1.544MHz or multiple thereof. Bits 1, 0 : Master Period Select 1, 0 (MPS[1:0]). In conjunction with the FREQSEL bit, these bits select the external MCLK frequency of the signal input at the MCLK pin of the DS26528. This is shown in Table 10-11.
Table 10-10. Backplane Reference Clock Select
BPREFSEL3 BPREFSEL2 BPREFSEL1 BPREFSEL0 BFREQSEL
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1
REFERENCE CLOCK SOURCE 2.048MHz RCLK1 1.544MHz RCLK1 2.048MHz RCLK2 1.544MHz RCLK2 2.048MHz RCLK3 1.544MHz RCLK3 2.048MHz RCLK4 1.544MHz RCLK4 2.048MHz RCLK5 1.544MHz RCLK5 2.048MHz RCLK6 1.544MHz RCLK6 2.048MHz RCLK7 1.544MHz RCLK7 2.048MHz RCLK8 1.544MHz RCLK8 1.544MHz derived from MCLK. (REFCLKIO is an output) 2.048MHz derived from MCLK. (REFCLKIO is an output) 2.048MHz External clock input at REFCLKIO (REFCLKIO is an input) 1.544MHz External clock input at REFCLKIO (REFCLKIO is an input)
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Table 10-11. Master Clock Input Selection
FREQSEL 0 0 0 0 1 1 1 1 MPS1 0 0 1 1 0 0 1 1 MPS0 0 1 0 1 0 1 0 1 MCLK (MHz 50ppm) 2.048 4.096 8.192 16.384 1.544 3.088 6.176 12.352
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DS26528 Octal T1/E1/J1 Transceiver Register Name:
Register Description: Register Address: Read/Write Function
GLSRR Global LIU Software Reset Register 0F5H R/W 6 LSRST7 0 5 LSRST6 0 4 LSRST5 0 3 LSRST4 0 2 LSRST3 0 1 LSRST2 0 0 LSRST1 0
Bit # Name Default
7 LSRST8 0
Bit 7 : Channel 8 LIU Software Reset (LSRST8). LIU logic and registers are reset with a 0-to-1transition in this bit. The reset is released when a zero is written to this bit. 0 = Normal Operation 1 = Reset LIU Bit 6: Channel 7 LIU Software Reset (LSRST7). LIU logic and registers are reset with a 0-to-1transition in this bit. The reset is released when a zero is written to this bit. 0 = Normal Operation 1 = Reset LIU Bit 5 : Channel 6 LIU Software Reset (LSRST6). LIU logic and registers are reset with a 0-to-1transition in this bit. The reset is released when a zero is written to this bit. 0 = Normal Operation 1 = Reset LIU Bit 4 : Channel 5 LIU Software Reset (LSRST5). LIU logic and registers are reset with a 0-to-1transition in this bit. The reset is released when a zero is written to this bit. 0 = Normal Operation 1 = Reset LIU Bit 3 : Channel 4 LIU Software Reset (LSRST4). LIU logic and registers are reset with a 0-to-1transition in this bit. The reset is released when a zero is written to this bit. 0 = Normal Operation 1 = Reset LIU Bit 2 : Channel 3 LIU Software Reset (LSRST3). LIU logic and registers are reset with a 0-to-1transition in this bit. The reset is released when a zero is written to this bit. 0 = Normal Operation 1 = Reset LIU Bit 1 : Channel 2 LIU Software Reset (LSRST2). LIU logic and registers are reset with a 0-to-1transition in this bit. The reset is released when a zero is written to this bit. 0 = Normal Operation 1 = Reset LIU. Bit 0 : Channel 1 LIU Software Reset (LSRST1). LIU logic and registers are reset with a 0-to-1transition in this bit. The reset is released when a zero is written to this bit. 0 = Normal Operation 1 = Reset LIU
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DS26528 Octal T1/E1/J1 Transceiver Register Name:
Register Description: Register Address: Read/Write Function
GFSRR Global Framer and BERT Software Reset Register 0F6H R/W 6 FSRST7 0 5 FSRST6 0 4 FSRST5 0 3 FSRST4 0 2 FSRST3 0 1 FSRST2 0 0 FSRST1 0
Bit # Name Default
7 FSRST8 0
Bit 7 : Channel 8 Framer and BERT Software Reset (FSRST8). Framer logic and registers are reset with a 0-to1 transition in this bit. The reset is released when a zero is written to this bit. 0 = Normal Operation 1 = Reset Framer and BERT Bit 6: Channel 7 Framer and BERT Software Reset (FSRST7). Framer logic and registers are reset with a 0-to-1 transition in this bit. The reset is released when a zero is written to this bit. 0 = Normal Operation 1 = Reset Framer and BERT Bit 5 : Channel 6 Framer and BERT Software Reset (FSRST6). Framer logic and registers are reset with a 0-to1 transition in this bit. The reset is released when a zero is written to this bit. 0 = Normal Operation 1 = Reset Framer and BERT Bit 4 : Channel 5 Framer and BERT Software Reset (FSRST5). Framer logic and registers are reset with a 0-to1 transition in this bit. The reset is released when a zero is written to this bit. 0 = Normal Operation 1 = Reset Framer and BERT Bit 3 : Channel 4 Framer and BERT Software Reset (FSRST4). Framer logic and registers are reset with a 0-to1 transition in this bit. The reset is released when a zero is written to this bit. 0 = Normal Operation 1 = Reset Framer and BERT Bit 2 : Channel 3 Framer and BERT Software Reset (FSRST3). Framer logic and registers are reset with a 0-to1 transition in this bit. The reset is released when a zero is written to this bit. 0 = Normal Operation 1 = Reset Framer and BERT Bit 1 : Channel 2 Framer and BERT Software Reset (FSRST2). Framer logic and registers are reset with a 0-to1 transition in this bit. The reset is released when a zero is written to this bit. 0 = Normal Operation 1 = Reset Framer and BERT Bit 0 : Channel 1 Framer and BERT Software Reset (FSRST1). Framer logic and registers are reset with a 0-to1 transition in this bit. The reset is released when a zero is written to this bit. 0 = Normal Operation 1 = Reset Framer and BERT
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DS26528 Octal T1/E1/J1 Transceiver Register Name:
Register Description: Register Address: Read/Write Function
IDR Device Identification Register 0F8H R 6 ID6 1 5 ID5 0 4 ID4 1 3 ID3 1 2 ID2 0 1 ID1 0 0 ID0 1
Bit # Name Default
7 ID7 0
Bits 7 to 3: Device ID (ID3 to ID7). The upper five bits of the IDR are used to display the DS26528 ID.
Table 10-12. Device ID Codes in this Product Family
DEVICE DS26528 DS26524 DS26522 DS26521 ID7 0 0 0 0 ID6 1 1 1 1 ID5 0 1 1 1 ID4 1 0 0 1 ID3 1 0 1 0
Bits 2 to 0: Silicon Revision Bits (ID0 to ID2). The lower three bits of the IDR are used to display a sequential number denoting the die revision of the chip. The initial silicon revision = "000", and is incremented with each silicon revision. This value is not the same as the two-character device revision on the top brand of the device. This is due to the fact that portions of the device assembly other than the silicon may change, causing the device revision increment on the brand without having a revision of the silicon. IDO is the LSB of a decimal code that represents the chip revision.
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Register Name: Register Description: Register Address: Read/Write Function
GFISR Global Framer Interrupt Status Register 0F9H R 6 FIS7 0 5 FIS6 0 4 FIS5 0 3 FIS4 0 2 FIS3 0 1 FIS2 0 0 FIS1 0
Bit # Name Default
7 FIS8 0
The GFISR register reports the framer interrupt status for each of the 8 T1/E1 framers. A logic one in the associated bit location indicates a framer has set its interrupt signal. Bit 7 : Framer Interrupt Status 8 (FIS8). 0 = Framer 8 has not issued an interrupt. 1 = Framer 8 has issued an interrupt. Bit 6 : Framer Interrupt Status 7 (FIS7). 0 = Framer 7 has not issued an interrupt. 1 = Framer 7 has issued an interrupt. Bit 5 : Framer Interrupt Status 6 (FIS6). 0 = Framer 6 has not issued an interrupt. 1 = Framer 6 has issued an interrupt. Bit 4 : Framer Interrupt Status 5 (FIS5). 0 = Framer 5 has not issued an interrupt. 1 = Framer 5 has issued an interrupt. Bit 3 : Framer Interrupt Status 4 (FIS4). 0 = Framer 4 has not issued an interrupt. 1 = Framer 4 has issued an interrupt. Bit 2 : Framer Interrupt Status 3 (FIS3). 0 = Framer 3 has not issued an interrupt. 1 = Framer 3 has issued an interrupt. Bit 1 : Framer Interrupt Status 2 (FIS2). 0 = Framer 2 has not issued an interrupt. 1 = Framer 2 has issued an interrupt. Bit 0 : Framer Interrupt Status 1(FIS1). 0 = Framer 1 has not issued an interrupt. 1 = Framer 1 has issued an interrupt.
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address: Read/Write Function
GBISR Global BERT Interrupt Status Register 0FAH R 6 BIS7 0 5 BIS6 0 4 BIS5 0 3 BIS4 0 2 BIS3 0 1 BIS2 0 0 BIS1 0
Bit # Name Default
7 BIS8 0
The GBISR register reports the interrupt status for each of the 8 T1/E1 bit error rate testers (BERT). A logic one in the associated bit location indicates a BERT has set its interrupt signal. Bit 7 : BERT Interrupt Status 8 0 = BERT 8 has not issued an interrupt. 1 = BERT 8 has issued an interrupt. Bit 6 : BERT Interrupt Status 7 0 = BERT 7 has not issued an interrupt. 1 = BERT 7 has issued an interrupt. Bit 5 : BERT Interrupt Status 6 0 = BERT 6 has not issued an interrupt. 1 = BERT 6 has issued an interrupt. Bit 4 : BERT Interrupt Status 5 0 = BERT 5 has not issued an interrupt. 1 = BERT 5 has issued an interrupt. Bit 3 : BERT Interrupt Status 4 0 = BERT 4 has not issued an interrupt. 1 = BERT 4 has issued an interrupt. Bit 2 : BERT Interrupt Status 3 0 = BERT 3 has not issued an interrupt. 1 = BERT 3 has issued an interrupt. Bit 1 : BERT Interrupt Status 2 0 = BERT 2 has not issued an interrupt. 1 = BERT 2 has issued an interrupt. Bit 0 : BERT Interrupt Status 1 0 = BERT 1 has not issued an interrupt. 1 = BERT 1 has issued an interrupt.
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address: Read/Write Function
GLISR Global LIU Interrupt Status Register 0FBH R 6 LIS7 0 5 LIS6 0 4 LIS5 0 3 LIS4 0 2 LIS3 0 1 LIS2 0 0 LIS1 0
Bit # Name Default
7 LIS8 0
The GLISR register reports the LIU interrupt status for each of the 8 T1/E1 LIUs. A logic one in the associated bit location indicates a LIU has set its interrupt signal. Bit 7 : LIU Interrupt Status 8 0 = LIU 8 has not issued an interrupt. 1 = LIU 8 has issued an interrupt. Bit 6 : LIU Interrupt Status 7 0 = LIU 7 has not issued an interrupt. 1 = LIU 7 has issued an interrupt. Bit 5 : LIU Interrupt Status 6 0 = LIU 6 has not issued an interrupt. 1 = LIU 6 has issued an interrupt. Bit 4 : LIU Interrupt Status 5 0 = LIU 5 has not issued an interrupt. 1 = LIU 5 has issued an interrupt. Bit 3 : LIU Interrupt Status 4 0 = LIU 4 has not issued an interrupt. 1 = LIU 4 has issued an interrupt. Bit 2 : LIU Interrupt Status 3 0 = LIU 3 has not issued an interrupt. 1 = LIU 3 has issued an interrupt. Bit 1 : LIU Interrupt Status 2 0 = LIU 2 has not issued an interrupt. 1 = LIU 2 has issued an interrupt. Bit 0 : LIU Interrupt Status 1 0 = LIU 1 has not issued an interrupt. 1 = LIU 1 has issued an interrupt.
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address: Read/Write Function
GFIMR Global Framer Interrupt Mask Register 0FCH R/W 6 FIM7 0 5 FIM6 0 4 FIM5 0 3 FIM4 0 2 FIM3 0 1 FIM2 0 0 FIM1 0
Bit # Name Default
7 FIM8 0
Bit 7 : Framer 8 Interrupt Mask (FIM8). 0 = Interrupt masked. 1 = Interrupt enabled. Bit 6 : Framer 7 Interrupt Mask (FIM7). 0 = Interrupt masked. 1 = Interrupt enabled. Bit 5 : Framer 6 Interrupt Mask (FIM6). 0 = Interrupt masked. 1 = Interrupt enabled. Bit 4 : Framer 5 Interrupt Mask (FIM5). 0 = Interrupt masked. 1 = Interrupt enabled. Bit 3 : Framer 4 Interrupt Mask (FIM4). 0 = Interrupt masked. 1 = Interrupt enabled. Bit 2 : Framer 3 Interrupt Mask (FIM3). 0 = Interrupt masked. 1 = Interrupt enabled. Bit 1 : Framer 2 Interrupt Mask (FIM2). 0 = Interrupt masked. 1 = Interrupt enabled. Bit 0 : Framer 1 Interrupt Mask (FIM1). 0 = Interrupt masked. 1 = Interrupt enabled.
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address: Read/Write Function
GBIMR Global Bert Interrupt Mask Register 0FDH R/W 6 BIM7 0 5 BIM6 0 4 BIM5 0 3 BIM4 0 2 BIM3 0 1 BIM2 0 0 BIM1 0
Bit # Name Default
7 BIM8 0
Bit 7 : BERT Interrupt Mask 8 0 = Interrupt masked. 1 = Interrupt enabled. Bit 6 : BERT Interrupt Mask 7 0 = Interrupt masked. 1 = Interrupt enabled. Bit 5 : BERT Interrupt Mask 6 0 = Interrupt masked. 1 = Interrupt enabled. Bit 4 : BERT Interrupt Mask 5 0 = Interrupt masked. 1 = Interrupt enabled. Bit 3 : BERT Interrupt Mask 4 0 = Interrupt masked. 1 = Interrupt enabled. Bit 2 : BERT Interrupt Mask 3 0 = Interrupt masked. 1 = Interrupt enabled. Bit 1 : BERT Interrupt Mask 2 0 = Interrupt masked. 1 = Interrupt enabled. Bit 0 : BERT Interrupt Mask 1 0 = Interrupt masked. 1 = Interrupt enabled.
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address: Read/Write Function
GLIMR Global LIU Interrupt Mask Register 0FEH R/W 6 LIM7 0 5 LIM6 0 4 LIM5 0 3 LIM4 0 2 LIM3 0 1 LIM2 0 0 LIM1 0
Bit # Name Default
7 LIM8 0
Bit 7 : LIU Interrupt Mask 8 0 = Interrupt masked. 1 = Interrupt enabled. Bit 6 : LIU Interrupt Mask 7 0 = Interrupt masked. 1 = Interrupt enabled. Bit 5 : LIU Interrupt Mask 6 0 = Interrupt masked. 1 = Interrupt enabled. Bit 4 : LIU Interrupt Mask 5 0 = Interrupt masked. 1 = Interrupt enabled. Bit 3 : LIU Interrupt Mask 4 0 = Interrupt masked. 1 = Interrupt enabled. Bit 2 : LIU Interrupt Mask 3 0 = Interrupt masked. 1 = Interrupt enabled. Bit 1 : LIU Interrupt Mask 2 0 = Interrupt masked. 1 = Interrupt enabled. Bit 0 : LIU Interrupt Mask 1 0 = Interrupt masked. 1 = Interrupt enabled.
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DS26528 Octal T1/E1/J1 Transceiver
10.4 Framer Register Definitions
10.4.1 Receive Register Definitions
Register Name: Register Description: Register Address:
RHC Receive HDLC Control Register 010H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 RHR 0 5 RHMS 0 4 RHCS4 0 3 RHCS3 0 2 RHCS2 0 1 RHCS1 0 0 RHCS0 0
Bit # Name Default
7 RCRCD 0
Bit 7: Receive CRC16 Display (RCRCD). 0 = Do not write received CRC16 code to FIFO. (default) 1 = Write received CRC16 code to FIFO after last octet of packet. Bit 6: Receive HDLC Reset (RHR). Will reset the receive HDLC controller and flush the receive FIFO. Note that this bit is a acknowledged reset. The host should set this bit and the DS26528 will clear it once the reset operation is complete. The DS26528 will complete the HDLC reset within 2 frames. 0 = Normal operation 1 = Reset receive HDLC controller and flush the receive FIFO Bit 5: Receive HDLC Mapping Select (RHMS). 0 = Receive HDLC assigned to channels 1 = Receive HDLC assigned to FDL(T1 mode), Sa Bits(E1 mode) Bit 4 to 0 : Receive HDLC Channel Select 4 to 0 (RHCS[4:0]). These bits determine which DS0 is mapped to the HDLC controller when enabled with RHMS = 0. RHCS0 to RHCS4 = all 0s selects channel 1, RHCS0 to RHCS4 = all 1s selects channel 32 (E1). A change to the receive HDLC channel select is acknowledged only after a Receive HDLC Reset (RHR).
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RHBSE Receive HDLC Bit Suppress Register 011H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 BSE7 0 5 BSE6 0 4 BSE5 0 3 BSE4 0 2 BSE3 0 1 BSE2 0 0 BSE1 0
Bit # Name Default
7 BSE8 0
Bit 7 : Receive Channel Bit 8 Suppress (BSE8). MSB of the channel. Set to one to stop this bit from being used. Bit 6 : Receive Channel Bit 7 Suppress (BSE7). Set to one to stop this bit from being used. Bit 5 : Receive Channel Bit 6 Suppress (BSE6). Set to one to stop this bit from being used. Bit 4 : Receive Channel Bit 5 Suppress (BSE5). Set to one to stop this bit from being used. Bit 3 : Receive Channel Bit 4 Suppress (BSE4). Set to one to stop this bit from being used. Bit 2 : Receive Channel Bit 3 Suppress (BSE3). Set to one to stop this bit from being used. Bit 1 : Receive Channel Bit 2 Suppress (BSE2). Set to one to stop this bit from being used. Bit 0 : Receive Channel Bit 1 Suppress (BSE1). LSB of the channel. Set to one to stop this bit from being used.
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RDS0SEL Receive Channel Monitor Select 012H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 0 5 0 4 RCM4 0 3 RCM3 0 2 RCM2 0 1 RCM1 0 0 RCM0 0
Bit # Name Default
7 0
Bits 4 to 0 : Receive Channel Monitor Bits (RCM[4:0]). RCM0 is the LSB of a five bit channel select that determines which receive DS0 channel data will appear in the RDS0M register.
Register Name: Register Description: Register Address:
RSIGC Receive Signaling Control Register 013H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 0 5 0 4 RFSA1 CASMS 0 3 0 2 RSFF 0 1 RSFE 0 0 RSIE 0
Bit # Name Default
7 0
Bit 4 (T1 Mode): Receive Force Signaling All Ones (RFSA1). 0 = do not force robbed bit signaling to all ones 1 = force signaling bits to all ones on a per-channel basis according to the RSAOI1-RSAOI3 registers. Bit 4 (E1 Mode): CAS Mode Select (CASMS). 0 = The DS26528 will initiate a resync when two consecutive multiframe alignment signals have been received with an error. 1 = The DS26528 will initiate a resync when two consecutive multiframe alignment signals have been received with an error, or 1 multiframe has been received with all the bits in time slot 16 in state 0. Alignment criteria is met when at least one bit in state 1 is present in the time slot 16 preceding the multiframe alignment signal first detected (G.732 alternate criteria). Bit 2 : Receive Signaling Force Freeze (RSFF). Freezes receive side signaling at RSIG (and RSER if Receive Signaling Reinsertion is enabled); will override Receive Freeze Enable (RFE). 0 = do not force a freeze event 1 = force a freeze event Bit 1 : Receive Signaling Freeze Enable (RSFE). 0 = no freezing of receive signaling data will occur 1 = allow freezing of receive signaling data at RSIG (and RSER if Receive Signaling Reinsertion is enabled). Bit 0 : Receive Signaling Integration Enable (RSIE). 0 = signaling changes of state reported on any change in selected channels 1 = signaling must be stable for 3 multiframes in order for a change of state to be reported
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
T1RCR2 Receive Control Register 2 014H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 0 5 0 4 RSLC96 0 3 OOF2 0 2 OOF1 0 1 RAIIE 0 0 RD4RM 0
Bit # Name Default
7 0
Bit 4: Receive SLC-96 Synchronizer Enable (RSLC96). See Section 9.9.4.4 for SLC-96 details. 0 = the SLC-96 synchronizer is disabled 1 = the SLC-96 synchronizer is enabled Bits 3 to 2: Out Of Frame Select Bits (OOF[2:1]). OOF2 0 0 1 1 OOF1 0 1 0 1 OUT OF FRAME CRITERIA 2/4 frame bits in error 2/5 frame bits in error 2/6 frame bits in error 2/6 frame bits in error
Bit 1: Receive RAI Integration Enable (RAIIE). The ESF RAI indication can be interrupted for a period not to exceed 100ms per interruption (T1.403). In ESF mode, setting RAIIE will cause the RAI status from the DS26528 to be integrated for 200ms. 0 = RAI detects when 16 consecutive patterns of 00FF appear in the FDL. RAI clears when 14 or less patterns of 00FF hex out of 16 possible appear in the FDL 1 = RAI detects when the condition has been present for greater than 200ms. RAI clears when the condition has been absent for greater than 200ms. Bit 0: Receive Side D4 Remote Alarm Select (RD4RM). 0 = zeros in bit 2 of all channels 1 = a one in the S-bit position of frame 12 (J1 Yellow Alarm Mode)
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
E1RSAIMR Receive Sa Bit Interrupt Mask Register 014H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 0 5 0 4 Rsa4IM 0 3 Rsa5IM 0 2 Rsa6IM 0 1 Rsa7IM 0 0 Rsa8IM 0
Bit # Name Default
7 0
Bit 4: Sa4 Change Detect Interrupt Mask. This bit will enable the change detect interrupt for the Sa4 bits. Any change of state of the Sa4 bit will then generate an interrupt in RLS7.0 to indicate the change of state. 0 = Interrupt Masked. 1 = Interrupt Enabled. Bit 3: Sa5 Change Detect Interrupt Mask. This bit will enable the change detect interrupt for the Sa5 bits. Any change of state of the Sa5 bit will then generate an interrupt in RLS7.0 to indicate the change of state. 0 = Interrupt Masked. 1 = Interrupt Enabled. Bit 2: Sa6 Change Detect Interrupt Mask. This bit will enable the change detect interrupt for the Sa6 bits. Any change of state of the Sa6 bit will then generate an interrupt in RLS7.0 to indicate the change of state. 0 = Interrupt Masked. 1 = Interrupt Enabled. Bit 1: Sa7 Change Detect Interrupt Mask. This bit will enable the change detect interrupt for the Sa7 bits. Any change of state of the Sa7 bit will then generate an interrupt in RLS7.0 to indicate the change of state. 0 = Interrupt Masked. 1 = Interrupt Enabled. Bit 0: Sa8 Change Detect Interrupt Mask. This bit will enable the change detect interrupt for the Sa8 bits. Any change of state of the Sa8 bit will then generate an interrupt in RLS7.0 to indicate the change of state. 0 = Interrupt Masked. 1 = Interrupt Enabled.
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
T1RBOCC Receive BOC Control Register 015H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 0 5 RBD1 0 4 RBD0 0 3 0 2 RBF1 0 1 RBF0 0 0 0
Bit # Name Default
7 RBR 0
Bit 7: Receive BOC Reset (RBR). The host should set this bit to force a reset of the BOC circuitry. Note that this is an acknowledged reset - that is the host need only set the bit and the DS26528 will clear it once the reset operation is complete (less than 250us). Modifications to the RBF0, RBF1, RBD0, and RBD1 bits will not be applied to the BOC controller until a BOC reset has been completed. Bits 5, 4: Receive BOC Disintegration bits (RBD[1:0]). The BOC Disintegration filter sets the number of message bits that must be received without a valid BOC to set the BC bit indicating that a valid BOC is no longer being received. RBD1 0 0 1 1 RBD0 0 1 0 1 CONSECUTIVE MESSAGE BITS FOR BOC CLEAR IDENTIFICATION 16 32 48 1 64
Bits 2, 1: Receive BOC Filter bits (RBF[1:0). The BOC filter sets the number of consecutive patterns that must be received without error prior to an indication of a valid message. RBF1 0 0 1 1 RBF0 0 1 0 1 CONSECUTIVE BOC CODES FOR VALID SEQUENCE IDENTIFICATION None 3 5 1 7
Note: The DS26528's BOC controller does not integrate and disintegrate concurrently. Therefore, if the maximum integration time and the maximum disintegration time are used together, BOC messages which repeat fewer than 11 times may not be detected.
Register Name: Register Description: Register Address:
RIDR1 to RIDR32 Receive Idle Code Definition Registers 1 to 32 20H to 3FH + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0
Bit # Name Default
7 C7 0
Bits 7 to 0: Per-Channel Idle Code Bits (C[7:0]). C0 is the LSB of the Code (this bit is transmitted last). Address 20H is for channel 1. Address 37H is for channel 24. Address 3FH is for channel 32.
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
T1RSAOI1, T1RSAOI2, T1RSAOI3, Receive Signaling All Ones Insertion Registers 038H, 039H, 03AH + (200h x n): where n = 0 to 7, for Ports 1 to 8 (LSB) CH1 CH9 CH17
(MSB) CH8 CH16 CH24
CH7 CH15 CH23
CH6 CH14 CH22
CH5 CH13 CH21
CH4 CH12 CH20
CH3 CH11 CH19
CH2 CH10 CH18
T1RSAOI1 T1RSAOI2 T1RSAOI3
Setting any of the CH1 through CH24 bits in the RSAOI1 through RSAOI3 registers will cause signaling data to be replaced with logic ones as reported on RSER. The RSIG signal will continue to report received signaling data. Note that this feature must be enabled with control bit RSIGC.4.
Register Name: Register Description: Register Address:
T1RDMWE1, T1RDMWE2, T1RDMWE3 T1 Receive Digital Milliwatt Enable Registers 03CH, 03DH, 03EH + (200h x n): where n = 0 to 7, for Ports 1 to 8 (LSB) CH1 CH9 CH17
(MSB) CH8 CH16 CH24
CH7 CH15 CH23
CH6 CH14 CH22
CH5 CH13 CH21
CH4 CH12 CH20
CH3 CH11 CH19
CH2 CH10 CH18
T1RDMWE1 T1RDMWE2 T1RDMWE3
Bits 7 to 0: Receive Digital Milliwatt Enable for Channels 1 to 24 (CH1 to CH24). 0 =do not affect the receive data associated with this channel 1 = replace the receive data associated with this channel with digital milliwatt code
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RS1 to RS12 Receive Signaling Registers 040H to 04FH + (200h x n): where n = 0 to 7, for Ports 1 to 8 (LSB) CH13-D CH14-D CH15-D CH16-D CH17-D CH18-D CH19-D CH20-D CH21-D CH22-D CH23-D CH24-D (LSB) X CH16-D CH17-D CH18-D CH19-D CH20-D CH21-D CH22-D CH23-D CH24-D CH25-D CH26-D CH27-D CH28-D CH29-D CH30-D
T1 Mode: (MSB) CH1-A CH1-B CH2-A CH2-B CH3-A CH3-B CH4-A CH4-B CH5-A CH5-B CH6-A CH6-B CH7-A CH7-B CH8-A CH8-B CH9-A CH9-B CH10-A CH10-B CH11-A CH11-B CH12-A CH12-B E1 MODE: (MSB) 0 0 CH1-A CH1-B CH2-A CH2-B CH3-A CH3-B CH4-A CH4-B CH5-A CH5-B CH6-A CH6-B CH7-A CH7-B CH8-A CH8-B CH9-A CH9-B CH10-A CH10-B CH11-A CH11-B CH12-A CH12-B CH13-A CH13-B CH14-A CH14-B CH15-A CH15-B
CH1-C CH2-C CH3-C CH4-C CH5-C CH6-C CH7-C CH8-C CH9-C CH10-C CH11-C CH12-C
CH1-D CH2-D CH3-D CH4-D CH5-D CH6-D CH7-D CH8-D CH9-D CH10-D CH11-D CH12-D
CH13-A CH14-A CH15-A CH16-A CH17-A CH18-A CH19-A CH20-A CH21-A CH22-A CH23-A CH24-A
CH13-B CH14-B CH15-B CH16-B CH17-B CH18-B CH19-B CH20-B CH21-B CH22-B CH23-B CH24-B
CH13-C CH14-C CH15-C CH16-C CH17-C CH18-C CH19-C CH20-C CH21-C CH22-C CH23-C CH24-C
RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12
0 CH1-C CH2-C CH3-C CH4-C CH5-C CH6-C CH7-C CH8-C CH9-C CH10-C CH11-C CH12-C CH13-C CH14-C CH15-C
0 CH1-D CH2-D CH3-D CH4-D CH5-D CH6-D CH7-D CH8-D CH9-D CH10-D CH11-D CH12-D CH13-D CH14-D CH15-D
X CH16-A CH17-A CH18-A CH19-A CH20-A CH21-A CH22-A CH23-A CH24-A CH25-A CH26-A CH27-A CH28-A CH29-A CH30-A
Y CH16-B CH17-B CH18-B CH19-B CH20-B CH21-B CH22-B CH23-B CH24-B CH25-B CH26-B CH27-B CH28-B CH29-B CH30-B
X CH16-C CH17-C CH18-C CH19-C CH20-C CH21-C CH22-C CH23-C CH24-C CH25-C CH26-C CH27-C CH28-C CH29-C CH30-C
RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12 RS13 RS14 RS15 RS16
In the ESF framing mode, there can be up to four signaling bits per channel (A, B, C, and D). In the D4 framing mode, there are only two signaling bits per channel (A and B). In the D4 framing mode, the framer will repeat the A and B signaling data in the C and D bit locations. Therefore, when the framer is operated in D4 framing mode, the user will need to retrieve the signaling bits every 1.5ms as opposed to 3ms for ESF mode. The Receive Signaling Registers are frozen and not updated during a loss of sync condition. They will contain the most recent signaling information before the "OOF" occurred.
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
LCVCR1 Line Code Violation Count Register 1 050H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 LCVC14 0 5 LCVC13 0 4 LCVC12 0 3 LCVC11 0 2 LCVC10 0 1 LCVC9 0 0 LCCV8 0
Bit # Name Default
7 LCVC15 0
Bits 7 to 0 : Line Code Violation Counter Bits 15 to 8 (LCVC15 to LCVC8). LCV15 is the MSB of the 16-bit code violation count
Register Name: Register Description: Register Address: Bit # Name Default 7 LCVC7 0
LCVCR2 Line Code Violation Count Register 2 051H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 LCVC6 0 5 LCVC5 0 4 LCVC4 0 3 LCVC3 0 2 LCVC2 0 1 LCVC1 0 0 LCVC0 0
Bits 7 to 0 : Line Code Violation Counter Bits 7 to 0 (LCVC7 to LCVC0). LCV0 is the LSB of the 16-bit code violation count
Register Name: Register Description: Register Address:
PCVCR1 Path Code Violation Count Register 1 052H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 PCVC14 0 5 PCVC13 0 4 PCVC12 0 3 PCVC11 0 2 PCVC10 0 1 PCVC9 0 0 PCVC8 0
Bit # Name Default
7 PCVC15 0
Bits 7 to 0 : Path Code Violation Counter Bits 15 to 8 (PCVC15 to PCVC8). PCVC15 is the MSB of the 16-bit path code violation count
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
PCVCR2 Path Code Violation Count Register 2 053H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 PCVC6 0 5 PCVC5 0 4 PCVC4 0 3 PCVC3 0 2 PCVC2 0 1 PCVC1 0 0 PCVC0 0
Bit # Name Default
7 PCVC7 0
Bits 7 to 0: Path Code Violation Counter Bits 0 to 7 (PCVC7 to PCVC0). PCVC0 is the LSB of the 16-bit path code violation count.
Register Name: Register Description: Register Address:
FOSCR1 Frames Out Of Sync Count Register 1 054H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 FOS14 0 5 FOS13 0 4 FOS12 0 3 FOS11 0 2 FOS10 0 1 FOS9 0 0 FOS8 0
Bit # Name Default
7 FOS15 0
Bits 7 to 0: Frames Out of Sync Counter Bits 15 to 8 (FOS15 to FOS8). FOS15 is the MSB of the 16-bit frames out of sync count.
Register Name: Register Description: Register Address:
FOSCR2 Frames Out Of Sync Count Register 2 055H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 FOS6 0 5 FOS5 0 4 FOS4 0 3 FOS3 0 2 FOS2 0 1 FOS1 0 0 FOS0 0
Bit # Name Default
7 FOS7 0
Bits 7 to 0: Frames Out of Sync Counter Bits 7 to 0 (FOS7 to FOS0). FOS0 is the LSB of the 16-bit frames out of sync count. Register Name: Register Description: Register Address: Bit # Name Default 7 EB15 0 E1EBCR1 E-Bit Count Register 1 056H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 EB14 0 5 EB13 0 4 EB12 0 3 EB11 0 2 EB10 0 1 EB9 0 0 EB8 0
Bits 7 to 0 : E-Bit Counter Bits 15 to 8 (EB[15:8]). EB15 is the MSB of the 16-bit E-Bit count
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DS26528 Octal T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 EB7 0 E1EBCR2 E-Bit Count Register 2 057H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 EB6 0 5 EB5 0 4 EB4 0 3 EB3 0 2 EB2 0 1 EB1 0 0 EB0 0
Bits 7 to 0 : E-Bit Counter Bits 7 to 0 (EB[7:0]). EB0 is the LSB of the 16-bit E-Bit count
Register Name: Register Description: Register Address:
RDS0M Receive DS0 Monitor Register 060H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 B2 0 5 B3 0 4 B4 0 3 B5 0 2 B6 0 1 B7 0 0 B8 0
Bit # Name Default
7 B1 0
Bits 7 to 0: Receive DS0 Channel Bits (B1 to B8). Receive channel data that has been selected by the Receive Channel Monitor Select Register. B8 is the LSB of the DS0 channel (last bit to be received).
Register Name: Register Description: Register Address:
E1RFRID Receive Firmware Revision ID Register 061H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 FR6 0 5 FR5 0 4 FR4 0 3 FR3 0 2 FR2 0 1 FR1 0 0 FR0 0
Bit # Name Default
7 FR7 0
Bits 7 to 0 : Firmware Revision (FR[7:0]). This read-only register reports the current revision of the receive firmware.
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
T1RFDL Receive FDL Register - T1 MODE 062H + (200h x n): where n = 0 to 7, for Ports 1 to 8 1 RFDL1 0 0 RFDL0 0
Bit # 7 6 5 4 3 2 Name RFDL7 RFDL6 RFDL5 RFDL4 RFDL3 RFDL2 Default 0 0 0 0 0 0 Note: This register has an alternate definition for E1 mode. See E1RRTS7. Bit 7: Receive FDL Bit 7 (RFDL7). MSB of the Received FDL Code. Bit 6: Receive FDL Bit 6 (RFDL6). Bit 5: Receive FDL Bit 5 (RFDL5). Bit 4: Receive FDL Bit 4 (RFDL4). Bit 3: Receive FDL Bit 3 (RFDL3). Bit 2: Receive FDL Bit 2 (RFDL2). Bit 1: Receive FDL Bit 1 (RFDL1). Bit 0: Receive FDL Bit 0 (RFDL0). LSB of the Received FDL Code.
Register Name: Register Description: Register Address:
E1RRTS7 Receive Real-Time Status Register 7 - E1 MODE 062H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 CSC4 5 CSC3 4 CSC2 3 CSC0
Bit # Name
2 1 0 CRC4S CASSA FASSA A Default 0 0 0 0 0 0 0 0 Note: This register has an alternate definition for T1 mode. See T1RFDL. All bits in this register are real-time (not latched). Bits 7 to 3 : CRC4 Sync Counter Bits (CSC[5:2} & CSC0). The CRC4 Sync Counter increments each time the 8 ms CRC4 multiframe search times out. The counter is cleared when the framer has successfully obtained synchronization at the CRC4 level. The counter can also be cleared by disabling the CRC4 mode (RCR1.3 = 0). This counter is useful for determining the amount of time the framer has been searching for synchronization at the CRC4 level. ITU G.706 suggests that if synchronization at the CRC4 level cannot be obtained within 400 ms, then the search should be abandoned and proper action taken. The CRC4 Sync Counter will saturate (not rollover). CSC0 is the LSB of the 6-bit counter. (Note: The next to LSB is not accessible. CSC1 is omitted to allow resolution to >400ms using 5 bits) Bit 2 : CRC4 MF Sync Active (CRC4SA). Set while the synchronizer is searching for the CRC4 MF alignment word. Bit 1 : CAS MF Sync Active (CASSA). Set while the synchronizer is searching for the CAS MF alignment word. Bit 0 : FAS Sync Active (FASSA). Set while the synchronizer is searching for alignment at the FAS level.
7 CSC5
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
T1RBOC Receive BOC Register 63H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 0 5 RBOC5 0 4 RBOC4 0 3 RBOC3 0 2 RBOC2 0 1 RBOC1 0 0 RBOC0 0
Bit # Name Default
7 0
Bit 5: BOC Bit 5 (RBOC5). Bit 4: BOC Bit 4 (RBOC4). Bit 3: BOC Bit 3 (RBOC3). Bit 2: BOC Bit 2 (RBOC2). Bit 1: BOC Bit 1 (RBOC1). Bit 0: BOC Bit 0 (RBOC0). The RBOC Register always contains the last valid BOC received. The Receive FDL Register (RFDL) reports the incoming Facility Data Link (FDL) or the incoming Fs bits. The LSB is received first. In D4 framing mode, RFDL updates on multiframe boundaries and reports the six Fs bits in RFDL0-RFDL5.
Register Name: Register Description: Register Address:
T1RSLC1, T1RSLC2, T1RSLC3 Receive SLC96 Data Link Registers - T1 MODE. 064H, 065H, 066H + (200h x n): where n = 0 to 7, for Ports 1 to 8
(MSB) (LSB) T1RSLC1 C8 C7 C6 C5 C4 C3 C2 C1 T1RSLC2 M2 M1 S=0 S=1 S=0 C11 C10 C9 T1RSLC3 S=1 S4 S3 S2 S1 A2 A1 M3 Note: These registers have an alternate definition for E1 mode. See E1RAF, E1RNAF, and E1RsiAF.
Register Name: Register Description: Register Address:
E1RAF E1 Receive Align Frame Register - E1 MODE 064H + (200h x n): where n = 0 to 7, for Ports 1 to 8 1 1 0 0 1 0
Bit # 7 6 5 4 3 2 Name Si 0 0 1 1 0 Default 0 0 0 0 0 0 Note: This register has an alternate definition for T1 mode. See T1RSLC1. Bit 7 : International Bit (Si). Bit 6 : Frame Alignment Signal Bit (0). Bit 5 : Frame Alignment Signal Bit (0). Bit 4 : Frame Alignment Signal Bit (1). Bit 3 : Frame Alignment Signal Bit (1). Bit 2 : Frame Alignment Signal Bit (0). Bit 1 : Frame Alignment Signal Bit (1). Bit 0 : Frame Alignment Signal Bit (1). 133 of 269
DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
E1RNAF E1 Receive Non-Align Frame Register - E1 MODE 065H + (200h x n): where n = 0 to 7, for Ports 1 to 8 1 Sa7 0 0 Sa8 0
Bit # 7 6 5 4 3 2 Name Si 1 A Sa4 Sa5 Sa6 Default 0 0 0 0 0 0 Note: This register has an alternate definition for T1 mode. See T1RSLC2. Bit 7 : International Bit (Si). Bit 6 : Frame Non-Alignment Signal Bit (1). Bit 5 : Remote Alarm (A). Bit 4 : Additional Bit 4 (Sa4). Bit 3 : Additional Bit 5 (Sa5). Bit 2 : Additional Bit 6 (Sa6). Bit 1 : Additional Bit 7 (Sa7). Bit 0 : Additional Bit 8 (Sa8).
Register Name: Register Description: Register Address:
E1RsiAF Received Si bits of the Align Frame - E1 MODE 066H + (200h x n): where n = 0 to 7, for Ports 1 to 8 1 SiF2 0 0 SiF0 0
Bit # 7 6 5 4 3 2 Name SiF14 SiF12 SiF10 SiF8 SiF6 SiF4 Default 0 0 0 0 0 0 Note: This register has an alternate definition for T1 mode. See T1RSLC3. Bit 7 : Si Bit of Frame 14 (SiF14). Bit 6 : Si Bit of Frame 12 (SiF12). Bit 5 : Si Bit of Frame 10 (SiF10). Bit 4 : Si Bit of Frame 8 (SiF8). Bit 3 : Si Bit of Frame 6 (SiF6). Bit 2 : Si Bit of Frame 4 (SiF4). Bit 1 : Si Bit of Frame 2 (SiF2). Bit 0 : Si Bit of Frame 0 (SiF0).
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
E1RSiNAF Received Si Bits of the Non-Align Frame 067H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 SiF13 0 5 SiF11 0 4 SiF9 0 3 SiF7 0 2 SiF5 0 1 SiF3 0 0 SiF1 0
Bit # Name Default
7 SiF15 0
Bit 7 : Si Bit of Frame 15 (SiF15). Bit 6 : Si Bit of Frame 13 (SiF13). Bit 5 : Si Bit of Frame 11 (SiF11). Bit 4 : Si Bit of Frame 9 (SiF9). Bit 3 : Si Bit of Frame 7 (SiF7). Bit 2 : Si Bit of Frame 5 (SiF5). Bit 1 : Si Bit of Frame 3 (SiF3). Bit 0 : Si Bit of Frame 1 (SiF1).
Register Name: Register Description: Register Address:
E1RRA Received Remote Alarm 068H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 RRAF13 0 5 RRAF11 0 4 RRAF9 0 3 RRAF7 0 2 RRAF5 0 1 RRAF3 0 0 RRAF1 0
Bit # Name Default
7 RRAF15 0
Bit 7 : Remote Alarm Bit of Frame 15 (RRAF15). Bit 6 : Remote Alarm Bit of Frame 13 (RRAF13). Bit 5 : Remote Alarm Bit of Frame 11 (RRAF11). Bit 4 : Remote Alarm Bit of Frame 9 (RRAF9). Bit 3 : Remote Alarm Bit of Frame 7 (RRAF7). Bit 2 : Remote Alarm Bit of Frame 5 (RRAF5). Bit 1 : Remote Alarm Bit of Frame 3 (RRAF3). Bit 0 : Remote Alarm Bit of Frame 1 (RRAF1).
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
E1RSa4 Received Sa4 Bits 069H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 RSa4F13 0 5 RSa4F11 0 4 RSa4F9 0 3 RSa4F7 0 2 RSa4F5 0 1 RSa4F3 0 0 RSa4F1 0
Bit # Name Default
7 RSa4F15 0
Bit 7 : Sa4 Bit of Frame 15 (RSa4F15). Bit 6 : Sa4 Bit of Frame 13 (RSa4F13). Bit 5 : Sa4 Bit of Frame 11 (RSa4F11). Bit 4 : Sa4 Bit of Frame 9 (RSa4F9). Bit 3 : Sa4 Bit of Frame 7 (RSa4F7). Bit 2 : Sa4 Bit of Frame 5 (RSa4F5). Bit 1 : Sa4 Bit of Frame 3 (RSa4F3). Bit 0 : Sa4 Bit of Frame 1 (RSa4F1).
Register Name: Register Description: Register Address:
E1RSa5 Received Sa5 Bits 06AH + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 RSa5F13 0 5 RSa5F11 0 4 RSa5F9 0 3 RSa5F7 0 2 RSa5F5 0 1 RSa5F3 0 0 RSa5F1 0
Bit # Name Default
7 RSa5F15 0
Bit 7 : Sa5 Bit of Frame 15 (RSa5F15). Bit 6 : Sa5 Bit of Frame 13 (RSa5F13). Bit 5 : Sa5 Bit of Frame 11 (RSa5F11). Bit 4 : Sa5 Bit of Frame 9 (RSa5F9). Bit 3 : Sa5 Bit of Frame 7 (RSa5F7). Bit 2 : Sa5 Bit of Frame 5 (RSa5F5). Bit 1 : Sa5 Bit of Frame 3 (RSa5F3). Bit 0 : Sa5 Bit of Frame 1 (RSa5F1).
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
E1RSa6 Received Sa6 Bits 06BH + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 RSa6F13 0 5 RSa6F11 0 4 RSa6F9 0 3 RSa6F7 0 2 RSa6F5 0 1 RSa6F3 0 0 RSa6F1 0
Bit # Name Default
7 RSa6F15 0
Bit 7 : Sa6 Bit of Frame 15 (RSa6F15). Bit 6 : Sa6 Bit of Frame 13 (RSa6F13). Bit 5 : Sa6 Bit of Frame 11 (RSa6F11). Bit 4 : Sa6 Bit of Frame 9 (RSa6F9). Bit 3 : Sa6 Bit of Frame 7 (RSa6F7). Bit 2 : Sa6 Bit of Frame 5 (RSa6F5). Bit 1 : Sa6 Bit of Frame 3 (RSa6F3). Bit 0 : Sa6 Bit of Frame 1 (RSa6F1).
Register Name: Register Description: Register Address:
E1RSa7 Received Sa7 Bits 06CH + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 RSa7F13 0 5 RSa7F11 0 4 RSa7F9 0 3 RSa7F7 0 2 RSa7F5 0 1 RSa7F3 0 0 RSa7F1 0
Bit # Name Default
7 RSa7F15 0
Bit 7 : Sa7 Bit of Frame 15 (RSa4F15). Bit 6 : Sa7 Bit of Frame 13 (RSa7F13). Bit 5 : Sa7 Bit of Frame 11 (RSa7F11). Bit 4 : Sa7 Bit of Frame 9 (RSa7F9). Bit 3 : Sa7 Bit of Frame 7 (RSa7F7). Bit 2 : Sa7 Bit of Frame 5 (RSa7F5). Bit 1 : Sa7 Bit of Frame 3 (RSa7F3). Bit 0 : Sa7 Bit of Frame 1 (RSa7F1).
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
E1RSa8 Received Sa8 Bits 06DH + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 RSa8F13 0 5 RSa8F11 0 4 RSa8F9 0 3 RSa8F7 0 2 RSa8F5 0 1 RSa8F3 0 0 RSa8F1 0
Bit # Name Default
7 RSa8F15 0
Bit 7 : Sa8 Bit of Frame 15 (RSa8F15). Bit 6 : Sa8 Bit of Frame 13 (RSa8F13). Bit 5 : Sa8 Bit of Frame 11 (RSa8F11). Bit 4 : Sa8 Bit of Frame 9 (RSa8F9). Bit 3 : Sa8 Bit of Frame 7 (RSa8F7). Bit 2 : Sa8 Bit of Frame 5 (RSa8F5). Bit 1 : Sa8 Bit of Frame 3 (RSa8F3). Bit 0 : Sa8 Bit of Frame 1 (RSa8F1).
Register Name: Register Description: Register Address:
SaBITS Received SaX Bits 06EH + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 RSa8F13 0 5 RSa8F11 0 4 RSa8F9 0 3 RSa8F7 0 2 RSa8F5 0 1 RSa8F3 0 0 RSa8F1 0
Bit # Name Default
7 RSa8F15 0
This register indicates the last received SaX bit. This can be used in conjunction with the RLS7 register to determine which SaX bits have changed. The user can program which Sa bit positions should be monitored via the E1RSAIMR register, and when a change is detected through an Interrupt in RSL6.0, the user can determine which bit has changed by reading this register and comparing it with previous known values. Bit 4 : Last Received Sa4 Bit. Bit 3 : Last Received Sa5 Bit. Bit 2 : Last Received Sa6 Bit. Bit 1 : Last Received Sa7 Bit. Bit 0 : Last Received Sa8 Bit.
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
Sa6CODE Received Sa6 Codeword 06FH + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 0 5 0 4 0 3 Sa6n 0 2 Sa6n 0 1 Sa6n 0 0 Sa6n 0
Bit # Name Default
7 0
This register will report the received Sa6 codeword per ETS300233. The bits are monitored on a sub-multiframe asynchronous basis, so the pattern reported could be one of multiple patterns that would represent a valid codeword. The table below indicates which patterns reported in this register correspond to a given valid Sa6 codeword. Bit 3 : Sa6 Codeword Bit. Bit 2 : Sa6 Codeword Bit. Bit 1 : Sa6 Codeword Bit. Bit 0 : Sa6 Codeword Bit. Valid Sa6 Code Sa6_8 Sa6_A Sa6_C Sa6_E Sa6_F Possible Reported Patterns 1000, 0100, 0010, 0001 1010, 0101 110, 0110, 0011, 1001 1110, 0111, 1011, 1101 1111
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RMMR Receive Master Mode Register 080H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 INIT_DONE 0 5 0 4 0 3 0 2 0 1 SFTRST 0 0 T1/E1 0
Bit # Name Default
7 FRM_EN 0
Bit 7: Framer Enable (FRM_EN). This bit must be set to the desired state before writing INIT_DONE. 0 = Framer disabled - held in low-power state 1 = Framer enabled - all features active Bit 6: Initialization Done (INIT_DONE). The user must set this bit once he has written the configuration registers. The host is required to write or clear all device registers prior to setting this bit. Once INIT_DONE is set, the DS26528 will check the FRM_EN bit and, if enabled will begin operation based on the initial configuration. Bit 1 : Soft Reset (SFTRST). Level sensitive `soft' reset. Should be taken high then low to reset the receiver. 0 = Normal operation 1 = Reset the receiver. Bit 0 : Receiver T1/E1 Mode Select (T1/E1). Sets operating mode for receiver only! This bit must be set to the desired state before writing INIT_DONE. 0 = T1 operation 1 = E1 operation
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RCR1 Receive Control Register 1 - T1 MODE 081H + (200h x n): where n = 0 to 7, for Ports 1 to 8 1 SYNCE 0 0 RESYNC 0
Bit # 7 6 5 4 3 2 Name SYNCT RB8ZS RFM ARC SYNCC RJC Default 0 0 0 0 0 0 Note: This register has an alternate definition for E1 mode. See RCR1. Bit 7 : Sync Time (SYNCT). 0 = qualify 10 bits 1 = qualify 24 bits Bit 6 : Receive B8ZS Enable (RB8ZS). 0 = B8ZS disabled 1 = B8ZS enabled Bit 5 : Receive Frame Mode Select (RFM). 0 = ESF framing mode 1 = D4 framing mode Bit 4 : Auto Resync Criteria (ARC). 0 = Resync on OOF or LOS event 1 = Resync on OOF only Bit 3 : Sync Criteria (SYNCC). In D4 Framing Mode. 0 = search for Ft pattern, then search for Fs pattern 1 = cross couple Ft and Fs pattern In ESF Framing Mode. 0 = search for FPS pattern only 1 = search for FPS and verify with CRC6 Bit 2 : Receive Japanese CRC6 Enable (RJC). 0 = use ANSI:AT&T:ITU CRC6 calculation (normal operation) 1 = use Japanese standard JT-G704 CRC6 calculation Bit 1 : Sync Enable (SYNCE). 0 = auto resync enabled 1 = auto resync disabled
Bit 0 : Resynchronize (RESYNC). When toggled from low to high, a resynchronization of the receive side framer is initiated. Must be cleared and set again for a subsequent resync.
141 of 269
DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RCR1 Receive Control Register 1 - E1 MODE 081H + (200h x n): where n = 0 to 7, for Ports 1 to 8 1 SYNCE 0 0 RESYNC 0
Bit # 7 6 5 4 3 2 Name RHDB3 RSIGM RG802 RCRC4 FRC Default 0 0 0 0 0 0 Note: This register has an alternate definition for T1 mode. See RCR1. Bit 6 : Receive HDB3 Enable (RHDB3). 0 = HDB3 disabled 1 = HDB3 enabled (decoded per O.162) Bit 5 : Receive Signaling Mode Select (RSIGM). 0 = CAS signaling mode 1 = CCS signaling mode Bit 4 : Receive G.802 Enable (RG802). See Section 19 for details. 0 = do not force RCHBLK high during bit 1 of time slot 26 1 = force RCHBLK high during bit 1 of time slot 26 Bit 3 : Receive CRC4 Enable (RCRC4). 0 = CRC4 disabled 1 = CRC4 enabled
Bit 2 : Frame Resync Criteria (FRC). 0 = resync if FAS received in error 3 consecutive times 1 = resync if FAS or bit 2 of non-FAS is received in error 3 consecutive times Bit 1 : Sync Enable (SYNCE). 0 = auto resync enabled 1 = auto resync disabled Bit 0 : Resynchronize (RESYNC). When toggled from low to high, a resynchronization of the receive side framer is initiated. Must be cleared and set again for a subsequent resync.
142 of 269
DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
T1RIBCC Receive In-Band Code Control Register - T1 MODE 082H + (200h x n): where n = 0 to 7, for Ports 1 to 8 1 RDN1 0 0 RDN0 0
Bit # 7 6 5 4 3 2 Name --RUP2 RUP1 RUP0 RDN2 Default 0 0 0 0 0 0 Note: This register has an alternate definition for E1 mode. See E1RCR2. Bits 5 to 3 : Receive Up Code Length Definition Bits (RUP2 to RUP0). RUP2 0 0 0 0 1 1 1 1 RUP1 0 0 1 1 0 0 1 1 RUP0 0 1 0 1 0 1 0 1 LENGTH SELECTED 1 bits 2 bits 3 bits 4 bits 5 bits 6 bits 7 bits 8 : 16 bits
Bits 2 to 0 : Receive Down Code Length Definition Bits (RDN2 to RDN0). RDN2 0 0 0 0 1 1 1 1 RDN1 0 0 1 1 0 0 1 1 RDN0 0 1 0 1 0 1 0 1 LENGTH SELECTED 1 bits 2 bits 3 bits 4 bits 5 bits 6 bits 7 bits 8 : 16 bits
143 of 269
DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
E1RCR2 Receive Control Register 2 - E1 MODE 082H+ (200h x n): where n = 0 to 7, for Ports 1 to 8 1 0 0 RLOSA 0
Bit # 7 6 5 4 3 2 Name RSa8S RSa7S RSa6S RSa5S RSa4S Default 0 0 0 0 0 0 Note: This register has an alternate definition for T1 mode. See T1RIBCC.
Bit 7 : Sa8 Bit Select (Sa8S). Set to one to have RLCLK pulse at the Sa8 bit position; set to zero to force RLCLK low during Sa8 bit position. Bit 6 : Sa7 Bit Select (Sa7S). Set to one to have RLCLK pulse at the Sa7 bit position; set to zero to force RLCLK low during Sa7 bit position. Bit 5 : Sa6 Bit Select (Sa6S). Set to one to have RLCLK pulse at the Sa6 bit position; set to zero to force RLCLK low during Sa6 bit position. Bit 4 : Sa5 Bit Select (Sa5S). Set to one to have RLCLK pulse at the Sa5 bit position; set to zero to force RLCLK low during Sa5 bit position. Bit 3 : Sa4 Bit Select (Sa4S). Set to one to have RLCLK pulse at the Sa4 bit position; set to zero to force RLCLK low during Sa4 bit position. Bit 0 : Receive Loss of Signal Alternate Criteria (RLOSA). Defines the criteria for a Loss of Signal condition. 0 = LOS declared upon 255 consecutive zeros (125ms) 1 = LOS declared upon 2048 consecutive zeros (1ms)
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RCR3 Receive Control Register 3 083H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 0 5 RSERC 0 4 0 3 0 2 0 1 PLB 0 0 FLB 0
Bit # Name Default
7 IDF 0
Bit 7 : Input Data Format (IDF). 0 = Bipolar data is expected at RTIP and RRING (either AMI or B8ZS) 1 = NRZ data is expected at RTIP. The BPV counter will be disabled and RRING will be ignored by the DS26528. Bit 5 : RSER Control (RSERC). 0 = allow RSER to output data as received under all conditions (normal operation) 1 = force RSER to one under loss of frame alignment conditions Bit 1 : Payload Loopback (PLB). 0 = loopback disabled 1 = loopback enabled When PLB is enabled, the following will occur: 1. 2. 3. 4. 5. data will be transmitted from the TTIP and TRING pins synchronous with RCLK instead of TCLK all of the receive side signals will continue to operate normally the TCHCLK and TCHBLK signals are forced low data at the TSER, TDATA, and TSIG pins is ignored the TLCLK signal will become synchronous with RCLK instead of TCLK.
In a PLB situation, the DS26528 will loop the 192 bits (248 for E1) of pay-load data (with BPVs corrected) from the receive section back to the transmit section. The transmitter will follow the frame alignment provided by the receiver. The receive frame boundary is automatically fed into the transmit section, such that the transmit frame position is locked to the receiver (i.e., TSYNC is sourced from RSYNC). The FPS framing pattern, CRC6 calculation, and the FDL bits (FAS word, Si, Sa, E-bits, and CRC4 for E1) are not looped back, they are reinserted by the DS26528 (i.e., the transmit section will modify the payload as if it was input at TSER). Bit 0 : Framer Loopback (FLB). 0 = loopback disabled 1 = loopback enabled This loopback is useful in testing and debugging applications. In FLB, the DS26528 will loop data from the transmit side back to the receive side. When FLB is enabled, the following will occur: 1. 2. 3. (T1 mode) an unframed all-ones code will be transmitted at TTIP and TRING (E1 mode) normal data will be transmitted at TTIP and TRING Data at RTIP and RRING will be ignored All receive side signals will take on timing synchronous with TCLK instead of RCLK. Note that it is not acceptable to have RCLK tied to TCLK during this loopback because this will cause an unstable condition.
145 of 269
DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RIOCR Receive I/O Configuration Register 084H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6
RSYNCINV
Bit # Name Default
7
RCLKINV
5
H100EN
4
RSCLKM
0
0
0
0
3 RSMS 0
2 RSIO 1
1 RSMS2 0
0 RSMS1 0
Bit 7 : RCLK Invert (RCLKINV). 0 = No inversion 1 = Invert RCLK as input Bit 6 : RSYNC Invert (RSYNCINV). 0 = No inversion 1 = Invert RSYNC as either input or output Bit 5 : H.100 SYNC Mode (H100EN). See Section 9.8.3 for more information. 0 = Normal operation 1 = RSYNC and TSSYNCIO signals are shifted Bit 4 : RSYSCLK Mode Select (RSCLKM). 0 = if RSYSCLK is 1.544MHz 1 = if RSYSCLK is 2.048MHz or IBO enabled Bit 3 : RSYNC Multiframe Skip Control (RSMS). T1 Mode ONLY. Useful in framing format conversions from D4 to ESF. This function is not available when the receive side elastic store is enabled. RSYNC must be set to output multiframe pulses. 0 = RSYNC will output a pulse at every multiframe 1 = RSYNC will output a pulse at every other multiframe Bit 2 : RSYNC I/O Select (RSIO). (Note: this bit must be set to zero when elastic store is disabled) The default value for this bit is a logic 1 so that the default state of RSYNC is as an input. 0 = RSYNC is an output 1 = RSYNC is an input (only valid if elastic store enabled) Bit 1 : RSYNC Mode Select 2 (RSMS2). T1: RSYNC pin must be programmed in the output frame mode 0 = do not pulse double wide in signaling frames 1 = do pulse double wide in signaling frames E1: RSYNC pin must be programmed in the output multiframe mode 0 = RSYNC outputs CAS multiframe boundaries 1 = RSYNC outputs CRC4 multiframe boundaries In E1 mode, RSMS2 also selects which multiframe signal is available at the RMSYNC pin, regardless of the configuration for RSYNC. When RSMS2 = 0, RMSYNC outputs CAS multiframe boundaries; when RSMS2 = 1, RMSYNC outputs CRC4 multiframe boundaries. Bit 0 : RSYNC Mode Select 1 (RSMS1). Selects frame or multiframe pulse when RSYNC pin is in output mode. In input mode (elastic store must be enabled) multiframe mode is only useful when receive signaling reinsertion is enabled. 0 = frame mode 1 = multiframe mode
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RESCR Receive Elastic Store Control Register 085H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6
RGCLKEN
Bit # Name Default
7
RDATFMT
0
0
5 0
4 RSZS 0
3
RESALGN
0
2 RESR 0
1
RESMDM
0
0 RESE 0
Bit 7 : Receive Channel Data Format (RDATFMT). 0 = 64KBps (data contained in all 8 bits) 1 = 56KBps (data contained in 7 out of the 8 bits) Bit 6 : Receive Gapped Clock Enable (RGCLKEN). 0 = RCHCLK functions normally 1 = Enable gapped bit clock output on RCHCLK RGPCKEN and RDATFMT are not associated with the elastic store and will be explained in the fractional support section. Bit 4 : Receive Slip Zone Select (RSZS). This bit determines the minimum distance allowed between the elastic store read and write pointers before forcing a controlled slip. This bit is only applies during T1 to E1 or E1 to T1 conversion applications. 0 = force a slip at 9 bytes or less of separation (used for clustered blank channels) 1 = force a slip at 2 bytes or less of separation (used for distributed blank channels and minimum delay mode) Bit 3 : Receive Elastic Store Align (RESALGN). Setting this bit from a zero to a one will force the receive elastic store's write/read pointers to a minimum separation of half a frame. No action will be taken if the pointer separation is already greater or equal to half a frame. If pointer separation is less than half a frame, the command will be executed and the data will be disrupted. Should be toggled after RSYSCLK has been applied and is stable. Must be cleared and set again for a subsequent align. Bit 2 : Receive Elastic Store Reset (RESR). Setting this bit from a zero to a one will force the read pointer into the same frame that the write pointer is exiting, minimizing the delay through the elastic store. If this command should place the pointers within the slip zone (see bit 4), then an immediate slip will occur and the pointers will move back to opposite frames. Should be toggled after RSYSCLK has been applied and is stable. Do not leave this bit set HIGH. Bit 1 : Receive Elastic Store Minimum Delay Mode (RESMDM). 0 = elastic stores operate at full two frame depth 1 = elastic stores operate at 32-bit depth Bit 0 : Receive Elastic Store Enable (RESE). 0 = elastic store is bypassed 1 = elastic store is enabled
147 of 269
DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
ERCNT Error Counter Configuration Register 086H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 MCUS 0 5 MECU 0 4 ECUS 0 3 EAMS 0 2 FSBE 0 1
MOSCR F
Bit # Name Default
7 1SECS 0
0 LCVCRF 0
0
Bit 7 / One-Second Select (1SECS). This bit allows for synchronization of the error counter updates between multiple ports. When ERCNT.3=0, setting this bit (on a specific framer) will update the framer's error counters on the transition of the one-second timer from framer #1. Note that this bit should always be clear for framer #1. 0 = Use the one-second timer that is internal to the framer. 1 = Use the one-second timer from framer #1 to latch updates. Bit 6 : Manual Counter Update Select (MCUS). When manual update mode is enabled with EAMS, this bit can be used to allow the incoming LATCH_CNT signal to latch all counters. Useful for synchronously latching counters of multiple DS26528 cores located on the same die. 0 = MECU is used to manually latch counters. 1 = Counters are latched on the rising edge of the LATCH_CNT signal. Bit 5 : Manual Error Counter Update (MECU). When enabled by ERCNT.3, the changing of this bit from a 0 to a 1 allows the next clock cycle to load the error counter registers with the latest counts and reset the counters. The user must wait a minimum of 250ms before reading the error count registers to allow for proper update. Bit 4 : Error Counter Update Select (ECUS). T1 mode: 0 = Update error counters once a second 1 = Update error counters every 42ms (333 frames) E1 mode: 0 = Update error counters once a second 1 = Update error counters every 62.5ms (500 frames) Bit 3 : Error Accumulation Mode Select (EAMS). 0 = Automatic updating of error counters enabled. The state of ERCNT.4 determines accumulation time (timed update) 1 = User toggling of ERCNT.5 determines accumulation time (manual update) Bit 2 : PCVCR Fs-Bit Error Report Enable (FSBE). T1 Mode Only. 0 = do not report bit errors in Fs-bit position; only Ft-bit position 1 = report bit errors in Fs-bit position as well as Ft-bit position Bit 1 : Multiframe Out of Sync Count Register Function Select (MOSCRF). T1 Mode Only. 0 = count errors in the framing bit position 1 = count the number of multiframes out of sync Bit 0 : T1 Line Code Violation Count Register Function Select (LCVCRF). 0 = do not count excessive zeros 1 = count excessive zeros
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RHFC Receive HDLC FIFO Control Register 087H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 0 5 0 4 0 3 0 2 0 1 RFHWM1 0 0 RFHWM0 0
Bit # Name Default
7 0
Bits 1 to 0 : Receive FIFO High Watermark Select (RFHWM1 to RFHWM0). RFHWM1 0 0 1 1 RFHWM0 0 1 0 1 Receive FIFO Watermark 4 bytes 16 bytes 32 bytes 48 bytes
149 of 269
DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RIBOC Receive Interleave Bus Operation Control Register 088H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 IBS1 0 5 IBS0 0 4 IBOSEL 0 3 IBOEN 0 2 DA2 0 1 DA1 0 0 DA0 0
Bit # Name Default
7 0
Bits 6 to 5 : IBO Bus Size bit 1 (IBS1 to IBS0). Indicates how many devices on the bus. IBS1 0 0 1 1 IBS0 0 1 0 1 Bus Size 2 Devices on bus (4.096MHz) 4 Devices on bus (8.192MHz) 8 Devices on bus (16.384MHz) Reserved for future use
Bit 4 : Interleave Bus Operation Select (IBOSEL). This bit selects channel or frame interleave mode. 0 = Channel Interleave 1 = Frame Interleave Bit 3 : Interleave Bus Operation Enable (IBOEN). 0 = Interleave Bus Operation disabled. 1 = Interleave Bus Operation enabled. Bits 2 to 0 : Device Assignment bits (DA2 to DA0). DA2 0 0 0 0 1 1 1 1 DA1 0 0 1 1 0 0 1 1 DA0 0 1 0 1 0 1 0 1 Device Position 1st Device on bus 2nd Device on bus 3rd Device on bus 4th Device on bus 5th Device on bus 6th Device on bus 7th Device on bus 8th Device on bus
150 of 269
DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
T1RSCC In-Band Receive Spare Control Register 089H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 0 5 0 4 0 3 0 2 RSC2 0 1 RSC1 0 0 RSC0 0
Bit # Name Default
7 0
Bits7 to 3 : Reserved, must be set to zero for proper operation Bits 2 to 0 : Receive Spare Code Length Definition Bits (RSC2 to RSC0). RSC2 0 0 0 0 1 1 1 1 RSC1 0 0 1 1 0 0 1 1 RSC0 0 1 0 1 0 1 0 1 LENGTH SELECTED 1 bits 2 bits 3 bits 4 bits 5 bits 6 bits 7 bits 8 : 16 bits
Register Name: Register Description: Register Address:
RXPC Receive eXpansion Port Control Register 08AH + (200h x n): where n = 0 to 7, for Ports 1 to 8 6
--
Bit # Name Default
7
--
5
--
4
--
0
0
0
0
3 -0
2 RBPDIR 0
1 RBPFUS 0
0 RBPEN 0
Bit 2 : Receive BERT Port Direction Control (RBPDIR). 0 = Normal (line) operation. Rx BERT port sources data from the receive path (RNRZ Data). 1 = System (Backplane) operation. Rx BERT port sources data from the transmit path. In this mode the data on RBPDATA becomes TDATA (transmit data on the line side of the e-store). The clock on RBPCLK becomes the clock that was generated for TBPCLK (must be referenced to TCLK). Bit 1 : Receive BERT Port Framed/Unframed Select (RBPFUS). T1 Mode Only. 0 = The DS26528's RBP_CLK will not clock data from the F-bit position (framed) 1 = The DS26528's RBP_CLK will clock data from the F-bit position (unframed) Bit 0 : Receive BERT Port Enable (RBPEN). 0 = Receive BERT Port is not active 1 = Receive BERT Port is active.
151 of 269
DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RBPBS Receive BERT Port Bit Suppress Register 08BH + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 BPBSE 7 0 5 BPBSE 6 0 4 BPBSE 5 0 3 BPBSE 4 0 2 BPBSE 3 0 1 BPBSE 2 0 0 BPBSE 1 0
Bit # Name Default
7 BPBSE8 0
Bit 7 : Receive Channel Bit 8 Suppress (BPBSE8). MSB of the channel. Set to one to stop this bit from being used. Bit 6 : Receive Channel Bit 7 Suppress (BPBSE7). Set to one to stop this bit from being used. Bit 5 : Receive Channel Bit 6 Suppress (BPBSE6). Set to one to stop this bit from being used. Bit 4 : Receive Channel Bit 5 Suppress (BPBSE5). Set to one to stop this bit from being used. Bit 3 : Receive Channel Bit 4 Suppress (BPBSE4). Set to one to stop this bit from being used. Bit 2 : Receive Channel Bit 3 Suppress (BPBSE3). Set to one to stop this bit from being used. Bit 1 : Receive Channel Bit 2 Suppress (BPBSE2). Set to one to stop this bit from being used. Bit 0 : Receive Channel Bit 1 Suppress (BPBSE1). LSB of the channel. Set to one to stop this bit from being used.
152 of 269
DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RLS1 Receive Latched Status Register 1 090H + (200h x n): where n = 0 to 7, for Ports 1 to 8 2 RAISD 0 1 RLOSD 0 0 RLOFD 0
Bit # 7 6 5 4 3 Name RRAIC RAISC RLOSC RLOFC RRAID Default 0 0 0 0 0 All bits in this register are latched and can create interrupts.
Bit 7 : Receive Remote Alarm Indication Condition Clear (RRAIC). Falling edge detect of RRAI. Set when a RRAI condition has cleared. Bit 6 : Receive Alarm Indication Signal Condition Clear (RAISC). Falling edge detect of RAIS. Set when a RAIS condition has cleared. Bit 5 : Receive Loss of Signal Condition Clear (RLOSC). Falling edge detect of RLOS. Set when an RLOS condition has cleared. Bit 4 : Receive Loss of Frame Condition Clear (RLOFC). Falling edge detect of RLOF. Set when an RLOF condition has cleared. Bit 3 : Receive Remote Alarm Indication Condition Detect (RRAID). Rising edge detect of RRAI. Set when a remote alarm is received at RTIP and RRING. Bit 2 : Receive Alarm Indication Signal Condition Detect (RAISD). Rising edge detect of RAIS.Set when an unframed all one's code is received at RTIP and RRING. Bit 1 : Receive Loss of Signal Condition Detect (RLOSD). Rising edge detect of RLOS. Set when 192 consecutive zeros have been detected at RTIP and RRING. Bit 0 : Receive Loss of Frame Condition Detect (RLOFD). Rising edge detect of RLOF. Set when the DS26528 has lost synchronized to the received data stream.
153 of 269
DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RLS2 - T1 Mode Receive Latched Status Register 2 091H + (200h x n): where n = 0 to 7, for Ports 1 to 8 1 B8ZS 0 0 FBE 0
Bit # 7 6 5 4 3 2 Name RPDV COFA 8ZD 16ZD SEFE Default 0 0 0 0 0 0 All bits in these register are latched. This register does not create interrupts.
Bit 7 : Receive Pulse Density Violation Event (RPDV). Set when the receive data stream does not meet the ANSI T1.403 requirements for pulse density. Bit 5 : Change of Frame Alignment Event (COFA). Set when the last resync resulted in a change of frame or multiframe alignment. Bit 4 : Eight Zero Detect Event (8ZD). Set when a string of at least eight consecutive zeros (regardless of the length of the string) have been received at RTIP and RRING. Bit 3 : Sixteen Zero Detect Event (16ZD). Set when a string of at least sixteen consecutive zeros (regardless of the length of the string) have been received at RTIP and RRING. Bit 2 : Severely Errored Framing Event (SEFE). Set when 2 out of 6 framing bits (Ft or FPS) are received in error. Bit 1 : B8ZS Codeword Detect Event (B8ZS). Set when a B8ZS codeword is detected at RTIP and RRING independent of whether the B8ZS mode is selected or not. Useful for automatically setting the line coding. Bit 0 : Frame Bit Error Event (FBE). Set when a Ft (D4) or FPS (ESF) framing bit is received in error.
Register Name: Register Description: Register Address:
RLS2 - E1 Mode E1 Receive Latched Status Register 2 091H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 CRCRC 0 5 CASRC 0 4 FASRC 0 3 RSA1 0 2 RSA0 0 1 RCMF 0 0 RAF 0
Bit # Name Default
7 0
Note: All bits in this register are latched. Bits 0 - 3 can cause interrupts. There is no associated real-time register. Bit 6 : CRC Resync Criteria Met Event (CRCRC). Set when 915:1000 codewords are received in error. Bit 5 : CAS Resync Criteria Met Event (CASRC). Set when 2 consecutive CAS MF alignment words are received in error. Bit 4 : FAS Resync Criteria Met Event (FASRC). Set when 3 consecutive FAS words are received in error. Bit 3 : Receive Signaling All Ones Event (RSA1). Set when the contents of time slot 16 contains less than three zeros over 16 consecutive frames. This alarm is not disabled in the CCS signaling mode. Bit 2 : Receive Signaling All Zeros Event (RSA0). Set when over a full MF, time slot 16 contains all zeros. Bit 1 : Receive CRC4 Multiframe Event (RCMF). Set on CRC4 multiframe boundaries; will continue to be set every 2 ms on an arbitrary boundary if CRC4 is disabled. Bit 0 : Receive Align Frame Event (RAF). Set approximately every 250ms to alert the host that Si and Sa bits are available in the RAF and RNAF registers. 154 of 269
DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RLS3 - T1 Mode Receive Latched Status Register 3 092H + (200h x n): where n = 0 to 7, for Ports 1 to 8 2 LSPD 0 1 LDND 0 0 LUPD 0
Bit # 7 6 5 4 3 Name LORCC LSPC LDNC LUPC LORCD Default 0 0 0 0 0 All bits in this register are latched and can create interrupts.
Bit 7 : Loss of Receive Clock Condition Clear (LORCC). Falling edge detect of LORC. Set when a LORC condition was detected and then removed. Bit 6 : Spare Code Detected Condition Clear (LSPC). Falling edge detect of LSP. Set when a spare-code match condition was detected and then removed. Bit 5 : Loop Down Code Detected Condition Clear (LDNC). Falling edge detect of LDN. Set when a loop-down condition was detected and then removed Bit 4 : Loop Up Code Detected Condition Clear (LUPC). Falling edge detect of LUP. Set when a loop-up condition was detected and then removed. Bit 3 : Loss of Receive Clock Condition Detect (LORCD). Rising edge detect of LORC. Set when the RCLK pin has not transitioned for one channel time. Bit 2 : Spare Code Detected Condition Detect (LSPD). Rising edge detect of LSP. Set when the spare code as defined in the RSCD1:2 registers is being received. Bit 1 : Loop Down Code Detected Condition Detect (LDND). Rising edge detect of LDN. Set when the loop down code as defined in the RDNCD1:2 register is being received. Bit 0 : Loop Up Code Detected Condition Detect (LUPD). Rising edge detect of LUP. Set when the loop up code as defined in the RUPCD1:2 register is being received.
155 of 269
DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RLS3 - E1 Mode Receive Latched Status Register 3 092H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 0 5 V52LNKC 0 4 RDMAC 0 3 LORCD 0 2 0 1 V52LNKD 0 0 RDMAD 0
Bit # Name Default
7 LORCC 0
Note: All bits in this register are latched and can create interrupts. Bit 7 : Loss of Receive Clock Clear (LORCC). Change of state indication. Set when a LORC condition has cleared (falling edge detect of LORC) Bit 5 : V5.2 Link Detected Clear (V52LNKC). Change of state indication. Set when a V52LNK condition has cleared (falling edge detect of V52LNK). Bit 4 : Receive Distant MF Alarm Clear (RDMAC). Change of state indication. Set when a RDMA condition has cleared (falling edge detect of RDMA). Bit 3 : Loss of Receive Clock Detect (LORCD). Change of state indication. Set when the RCLK pin has not transitioned for one channel time (rising edge detect of LORC). Bit 1 : V5.2 Link Detect (V52LNKD). Change of state indication. Set on detection of a V5.2 link identification signal. (G.965). This is the rising edge detect of V52LNK. Bit 0 : Receive Distant MF Alarm Detect (RDMAD). Change of state indication. Set when bit-6 of time slot 16 in frame 0 has been set for two consecutive multiframes. This alarm is not disabled in the CCS signaling mode. This is the rising edge detect of RDMA.
156 of 269
DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RLS4 Receive Latched Status Register 4 093H + (200h x n): where n = 0 to 7, for Ports 1 to 8 2 1SEC 0 1 TIMER 0 0 RMF 0
Bit # 7 6 5 4 3 Name RESF RESEM RSLIP RSCOS Default 0 0 0 0 0 All bits in this register are latched and can create interrupts.
Bit 7 : Receive Elastic Store Full Event (RESF). Set when the receive elastic store buffer fills and a frame is deleted. Bit 6 : Receive Elastic Store Empty Event (RESEM). Set when the receive elastic store buffer empties and a frame is repeated. Bit 5 : Receive Elastic Store Slip Occurrence Event (RSLIP). Set when the receive elastic store has either repeated or deleted a frame. Bit 3 : Receive Signaling Change Of State Event (RSCOS). Set when any channel selected by the Receive Signaling Change Of State Interrupt Enable registers (RSCSE1 through RSCSE3), changes signaling state. Bit 2 : One Second Timer (1SEC). Set on every 1 second interval based on RCLK. Bit 1 : Timer Event (TIMER). This status bit indicates that the performance monitor counters have been updated and are available to be read by the host. The error counter update interval as determined by the settings in the Error Counter Configuration Register (ERCNT). T1: Set on increments of 1 second or 42ms based on RCLK, or a manual latch event. E1: Set on increments of 1 second or 62.5ms based on RCLK, or a manual latch event. Bit 0 : Receive Multiframe Event (RMF). In T1 operation, set every 1.5ms on D4 MF boundaries or every 3ms on ESF MF boundaries. In E1 operation, set every 2.0ms on receive CAS multiframe boundaries to alert host the signaling data is available. Continues to set on an arbitrary 2.0ms boundary when CAS signaling is not enabled.
157 of 269
DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RLS5 Receive Latched Status Register 5 (HDLC) 094H + (200h x n): where n = 0 to 7, for Ports 1 to 8 2 RPS 0 1 RHWMS 0 0 RNES 0
Bit # 7 6 5 4 3 Name ROVR RHOBT RPE Default 0 0 0 0 0 All bits in this register are latched and can cause interrupts.
Bit 5 : Receive FIFO Overrun (ROVR). Set when the receive HDLC controller has terminated packet reception because the FIFO buffer is full. Bit 4 : Receive HDLC Opening Byte Event (RHOBT). Set when the next byte available in the receive FIFO is the first byte of a message. Bit 3 : Receive Packet End Event (RPE). Set when the HDLC controller detects either the finish of a valid message (i.e., CRC check complete) or when the controller has experienced a message fault such as a CRC checking error, or an overrun condition, or an abort has been seen. This is a latched bit and will be cleared when read. Bit 2 : Receive Packet Start Event (RPS). Set when the HDLC controller detects an opening byte. This is a latched bit and will be cleared when read. Bit 1 : Receive FIFO Above High Watermark Set Event (RHWMS). Set when the receive 64-byte FIFO crosses the high watermark as defined by the Receive HDLC FIFO Control Register (RHFC). Rising edge detect of RHWM. Bit 0 : Receive FIFO Not Empty Set Event (RNES). Set when the receive FIFO has transitioned from `empty' to `not-empty' (at least one byte has been put into the FIFO). Rising edge detect of RNE.
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RLS7 (T1 Mode) Receive Latched Status Register 7 096H + (200h x n): where n = 0 to 7, for Ports 1 to 8 2 RFDLF 0 1 BC 0 0 BD 0
Bit # 7 6 5 4 3 Name RRAI-CI RAIS-CI RSLC96 Default 0 0 0 0 0 All bits in this register are latched and can create interrupts.
Bit 5 : Receive RAI-CI Detect (RRAI-CI). Set when an RAI-CI pattern has been detected by the receiver (see Section). This bit is active in ESF framing mode only, and will set only if an RAI condition is being detected (RRTS1.3). When the host reads (and clears) this bit, it will set again each time the RAI-CI pattern is detected (approximately every 1.1 seconds). Bit 4 : Receive AIS-CI Detect (RAIS-CI). Set when an AIS-CI pattern has been detected by the receiver (see Section). This bit will set only if an AIS condition is being detected (RRTS1.2). This is a latched bit which must be cleared by the host, and will set again each time the AIS-CI pattern is detected (approximately every 1.2 seconds). Bit 3 : Receive SLC-96 Alignment Event (RSLC96). Set when a valid SLC-96 alignment pattern is detected in the Fs bit stream, and the RSLCx registers have data available for retrieval. See Section 9.9.4.4 for more information. Bit 2 : Receive FDL Register Full Event (RFDLF). Set when the 8-bit RFDL register is full. Useful for SLC-96 operation, or manual extraction of FDL data bits. See Section 9.9.5.4 for more information. Bit 1 : BOC Clear Event (BC). Set when a valid BOC is no longer detected (with the Disintegration filter applied). Bit 0 : BOC Detect Event (BD). Set when a valid BOC has been detected (with the BOC filter applied).
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RLS7 (E1 Mode) Receive Latched Status Register 7 096H + (200h x n): where n = 0 to 7, for Ports 1 to 8 2 0 1 Sa6CD 0 0 SaXCD 0
Bit # 7 6 5 4 3 Name Default 0 0 0 0 0 All bits in this register are latched and can create interrupts.
Bit 1 : Sa6 Codeword Detect. Set when a calid codeword (per ETS 300233) is detected in the Sa6 bit positions. Bit 0 : SaX Bit Change Detect. Set when a bit change is detected in the SaX bit position. The enabled SaX bits are selected by the E1RSAIMR register.
Register Name: Register Description: Register Address:
RSS1, RSS2, RSS3, RSS4 Receive Signaling Status Registers 098H, 099H, 09AH, 09BH + (200h x n): where n = 0 to 7, for Ports 1 to 8 (LSB) CH1* CH9 CH17* CH25
(MSB) CH8 CH16 CH24 CH32
CH7 CH15 CH23 CH31
CH6 CH14 CH22 CH30
CH5 CH13 CH21 CH29
CH4 CH12 CH20 CH28
CH3 CH11 CH19 CH27
CH2 CH10 CH18 CH26
RSS1 RSS2 RSS3 RSS4 (E1 mode)
Note: Status bits in this register are latched. When a channel's signaling data changes state, the respective bit in registers RSS1-RSS4 will be set and latched. The RSCOS bit (RLSR4.3) will be set if the channel was also enabled by setting the appropriate bit in RSCSE1-4. The INTB signal will go low if enabled by the interrupt mask bit RIM4.3. The bit will remain set until read. Note that in E1 CAS mode, the LSB of RSS1 would typically represent the CAS alignment bits, and the LSB of RSS3 represents reserved bits and the distant multiframe alarm.
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
T1RSCD1 Receive Spare Code Definition Register 1 09CH + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0
Bit # Name Default
7 C7 0
Note: Writing this register resets the detector's integration period. Bit 7 : Receive Spare Code Definition Bit 7 (C7). First bit of the repeating pattern. Bit 6 : Receive Spare Code Definition Bit 6 (C6). A Don't Care if a 1-bit length is selected. Bit 5 : Receive Spare Code Definition Bit 5 (C5). A Don't Care if a 1 or 2 bit length is selected. Bit 4 : Receive Spare Code Definition Bit 4 (C4). A Don't Care if a 1 to 3 bit length is selected. Bit 3 : Receive Spare Code Definition Bit 3 (C3). A Don't Care if a 1 to 4 bit length is selected. Bit 2 : Receive Spare Code Definition Bit 2 (C2). A Don't Care if a 1 to 5 bit length is selected. Bit 1 : Receive Spare Code Definition Bit 1 (C1). A Don't Care if a 1 to 6 bit length is selected. Bit 0 : Receive Spare Code Definition Bit 0 (C0). A Don't Care if a 1 to 7 bit length is selected.
Register Name: Register Description: Register Address:
T1RSCD2 Receive Spare Code Definition Register 2 09DH + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0
Bit # Name Default
7 C7 0
Bit 7 : Receive Spare Code Definition Bit 7 (C7). A Don't Care if a 1 to 7 bit length is selected. Bit 6 : Receive Spare Code Definition Bit 6 (C6). A Don't Care if a 1 to 7 bit length is selected. Bit 5 : Receive Spare Code Definition Bit 5 (C5). A Don't Care if a 1 to 7 bit length is selected. Bit 4 : Receive Spare Code Definition Bit 4 (C4). A Don't Care if a 1 to 7 bit length is selected. Bit 3 : Receive Spare Code Definition Bit 3 (C3). A Don't Care if a 1 to 7 bit length is selected. Bit 2 : Receive Spare Code Definition Bit 2 (C2). A Don't Care if a 1 to 7 bit length is selected. Bit 1 : Receive Spare Code Definition Bit 1 (C1). A Don't Care if a 1 to 7 bit length is selected. Bit 0 : Receive Spare Code Definition Bit 0 (C0). A Don't Care if a 1 to 7 bit length is selected.
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RIIR Receive Interrupt Information Register 9FH + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 RLS7 0 5 RLS6* 0 4 RLS5 0 3 RLS4 0 2 RLS3 0 1 RLS2** 0 0 RLS1 0
Bit # Name Default
7 0
* RLS6 is reserved for future use. ** Currently RLS2 does not create an interrupt therefore this bit is not used in T1 mode.
The Interrupt Information Registers indicate which of the DS26528 status registers are generating an interrupt. When an interrupt occurs, the host can read RIIR to quickly identify which of the receive status registers is (are) causing the interrupt(s). The Interrupt Information Register bits will clear once the appropriate interrupt has been serviced and cleared, as long as no additional, unmasked interrupt condition is present in the associated status register. Status bits that have been masked via the Receive Interrupt Mask (RIMx) registers, will also be masked from the RIIR register.
Register Name: Register Description: Register Address:
RIM1 Receive Interrupt Mask Register 1 0A0H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 RAISC 0 5 RLOSC 0 4 RLOFC 0 3 RRAID 0 2 RAISD 0 1 RLOSD 0 0 RLOFD 0
Bit # Name Default
7 RRAIC 0
Bit 7 : Receive Remote Alarm Indication Condition Clear (RRAIC). 0 = interrupt masked 1 = interrupt enabled Bit 6 : Receive Alarm Indication Signal Condition Clear (RAISC). 0 = interrupt masked 1 = interrupt enabled Bit 5 : Receive Loss of Signal Condition Clear (RLOSC). 0 = interrupt masked 1 = interrupt enabled Bit 4 : Receive Loss of Frame Condition Clear (RLOFC). 0 = interrupt masked 1 = interrupt enabled Bit 3 : Receive Remote Alarm Indication Condition Detect (RRAID). 0 = interrupt masked 1 = interrupt enabled Bit 2 : Receive Alarm Indication Signal Condition Detect (RAISD). 0 = interrupt masked 1 = interrupt enabled Bit 1 : Receive Loss of Signal Condition Detect (RLOSD). 0 = interrupt masked 1 = interrupt enabled Bit 0 : Receive Loss of Frame Condition Detect (RLOFD). 0 = interrupt masked 1 = interrupt enabled 162 of 269
DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RIM2 - E1 Mode Only E1 Receive Interrupt Mask Register 2 0A1H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 0 5 0 4 0 3 RSA1 0 2 RSA0 0 1 RCMF 0 0 RAF 0
Bit # Name Default
7 0
Bit 3 : Receive Signaling All Ones Event (RSA1). 0 = interrupt masked 1 = interrupt enabled Bit 2 : Receive Signaling All Zeros Event (RSA0). 0 = interrupt masked 1 = interrupt enabled Bit 1 : Receive CRC4 Multiframe Event (RCMF). 0 = interrupt masked 1 = interrupt enabled Bit 0 : Receive Align Frame Event (RAF). 0 = interrupt masked 1 = interrupt enabled
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RIM3 - T1 Mode Receive Interrupt Mask Register 3 0A2H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 LSPC 0 5 LDNC 0 4 LUPC 0 3 LORCD 0 2 LSPD 0 1 LDND 0 0 LUPD 0
Bit # Name Default
7 LORCC 0
Bit 7 : Loss of Receive Clock Condition Clear (LORCC). 0 = interrupt masked 1 = interrupt enabled Bit 6 : Spare Code Detected Condition Clear (LSPC). 0 = interrupt masked 1 = interrupt enabled Bit 5 : Loop Down Code Detected Condition Clear(LDNC). 0 = interrupt masked 1 = interrupt enabled Bit 4 : Loop Up Code Detected Condition Clear (LUPC). 0 = interrupt masked 1 = interrupt enabled Bit 3 : Loss of Receive Clock Condition Detect (LORCD). 0 = interrupt masked 1 = interrupt enabled Bit 2 : Spare Code Detected Condition Detect (LSPD). 0 = interrupt masked 1 = interrupt enabled Bit 1 : Loop Down Code Detected Condition Detect (LDND). 0 = interrupt masked 1 = interrupt enabled Bit 0 : Loop Up Code Detected Condition Detect (LUPD). 0 = interrupt masked 1 = interrupt enabled
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RIM3 - E1 Mode E1 Receive Interrupt Mask Register 3 0A2H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 0 5 V52LNKC 0 4 RDMAC 0 3 LORCD 0 2 0 1 V52LNKD 0 0 RDMAD 0
Bit # Name Default
7 LORCC 0
Bit 7 : Loss of Receive Clock Clear (LORCC). 0 = interrupt masked 1 = interrupt enabled Bit 5 : V5.2 Link Detected Clear (V52LNKC). 0 = interrupt masked 1 = interrupt enabled Bit 4 : Receive Distant MF Alarm Clear (RDMAC). 0 = interrupt masked 1 = interrupt enabled Bit 3 : Loss of Receive Clock Detect (LORCD). 0 = interrupt masked 1 = interrupt enabled Bit 1 : V5.2 Link Detect (V52LNKD). 0 = interrupt masked 1 = interrupt enabled Bit 0 : Receive Distant MF Alarm Detect (RDMAD). 0 = interrupt masked 1 = interrupt enabled
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RIM4 Receive Interrupt Mask Register 4 0A3H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 RESEM 0 5 RSLIP 0 4 0 3 RSCOS 0 2 1SEC 0 1 TIMER 0 0 RMF 0
Bit # Name Default
7 RESF 0
Bit 7 : Receive Elastic Store Full Event (RESF). 0 = interrupt masked 1 = interrupt enabled Bit 6 : Receive Elastic Store Empty Event (RESEM). 0 = interrupt masked 1 = interrupt enabled Bit 5 : Receive Elastic Store Slip Occurrence Event (RSLIP). 0 = interrupt masked 1 = interrupt enabled Bit 3 : Receive Signaling Change Of State Event (RSCOS). 0 = interrupt masked 1 = interrupt enabled Bit 2 : One Second Timer (1SEC). 0 = interrupt masked 1 = interrupt enabled Bit 1 : Timer Event (TIMER). 0 = interrupt masked 1 = interrupt enabled Bit 0 : Receive Multiframe Event (RMF). 0 = interrupt masked 1 = interrupt enabled
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RIM5 Receive Interrupt Mask 5 (HDLC) 0A4H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 0 5 ROVR 0 4 RHOBT 0 3 RPE 0 2 RPS 0 1 RHWMS 0 0 RNES 0
Bit # Name Default
7 0
Bit 5 : Receive FIFO Overrun (ROVR). 0 = interrupt masked 1 = interrupt enabled Bit 4 : Receive HDLC Opening Byte Event (RHOBT). 0 = interrupt masked 1 = interrupt enabled Bit 3 : Receive Packet End Event (RPE). 0 = interrupt masked 1 = interrupt enabled Bit 2 : Receive Packet Start Event (RPS). 0 = interrupt masked 1 = interrupt enabled Bit 1 : Receive FIFO Above High Watermark Set Event (RHWMS). 0 = interrupt masked 1 = interrupt enabled Bit 0 : Receive FIFO Not Empty Set Event (RNES). 0 = interrupt masked 1 = interrupt enabled
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RIM7 (T1 Mode) Receive Interrupt Mask Register 7 (BOC:FDL) A6H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 0 5 RRAI-CI 0 4 RAIS-CI 0 3 RSLC96 0 2 RFDLF 0 1 BC 0 0 BD 0
Bit # Name Default
7 0
Bit 5 : Receive RAI-CI (RRAI-CI). 0 = interrupt masked 1 = interrupt enabled Bit 4 : Receive AIS-CI (RAIS-CI). 0 = interrupt masked 1 = interrupt enabled Bit 3 : Receive SLC-96 (RSLC96). 0 = interrupt masked 1 = interrupt enabled Bit 2 : Receive FDL Register Full (RFDLF). 0 = interrupt masked 1 = interrupt enabled Bit 1 : BOC Clear Event (BC). 0 = interrupt masked 1 = interrupt enabled Bit 0 : BOC Detect Event (BD). 0 = interrupt masked 1 = interrupt enabled
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RIM7 (E1 Mode) Receive Interrupt Mask Register 7 (BOC:FDL) A6H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 0 5 0 4 0 3 0 2 0 1 Sa6CD 0 0 SaXCD 0
Bit # Name Default
7 0
Bit 1 : Sa6 Codeword Detect. This bit will enable the interrupt generated when a valid codeword (per ETS 300 233) is detected in the Sa6 bits. 0 = interrupt masked 1 = interrupt enabled Bit 0 : SaX Change Detect. This bit will enable the interrupt generated when a change of state is detected in any of the unmasked SaX bit positions. The masked or unmasked SaX bits are selected by the E1RSAIMR register. 0 = interrupt masked 1 = interrupt enabled
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RSCSE1, RSCSE2, RSCSE3, RSCSE4 Receive Signaling Change of State Enable 0A8H, 0A9H, 0AAH, 0ABH + (200h x n): where n = 0 to 7, for Ports 1 to 8 (LSB) CH1 CH9 CH17 CH25
(MSB) CH8 CH16 CH24 CH32
CH7 CH15 CH23 CH31
CH6 CH14 CH22 CH30
CH5 CH13 CH21 CH29
CH4 CH12 CH20 CH28
CH3 CH11 CH19 CH27
CH2 CH10 CH18 CH26
RSCSE1 RSCSE2 RSCSE3 RSCSE4 (E1 Only)
Setting any of the CH1 through CH32 bits in the RSS1 through RSS4 registers will cause RSCOS (RLSR4.3) to be set when that channel's signaling data changes state.
Register Name: Register Description: Register Address:
T1RUPCD1 Receive Up Code Definition Register 1 0ACH + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0
Bit # Name Default
7 C7 0
Note: Writing this register resets the detector's integration period. Bit 7 : Receive Up Code Definition Bit 7 (C7). First bit of the repeating pattern. Bit 6 : Receive Up Code Definition Bit 6 (C6). A Don't Care if a 1-bit length is selected. Bit 5 : Receive Up Code Definition Bit 5 (C5). A Don't Care if a 1 or 2 bit length is selected. Bit 4 : Receive Up Code Definition Bit 4 (C4). A Don't Care if a 1 to 3 bit length is selected. Bit 3 : Receive Up Code Definition Bit 3 (C3). A Don't Care if a 1 to 4 bit length is selected. Bit 2 : Receive Up Code Definition Bit 2 (C2). A Don't Care if a 1 to 5 bit length is selected. Bit 1 : Receive Up Code Definition Bit 1 (C1). A Don't Care if a 1 to 6 bit length is selected. Bit 0 : Receive Up Code Definition Bit 0 (C0). A Don't Care if a 1 to 7 bit length is selected.
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
T1RUPCD2 Receive Up Code Definition Register 2 0ADH + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0
Bit # Name Default
7 C7 0
Bit 7 : Receive Up Code Definition Bit 7 (C7). A Don't Care if a 1 to 7 bit length is selected. Bit 6 : Receive Up Code Definition Bit 6 (C6). A Don't Care if a 1 to 7 bit length is selected. Bit 5 : Receive Up Code Definition Bit 5 (C5). A Don't Care if a 1 to 7 bit length is selected. Bit 4 : Receive Up Code Definition Bit 4 (C4). A Don't Care if a 1 to 7 bit length is selected. Bit 3 : Receive Up Code Definition Bit 3 (C3). A Don't Care if a 1 to 7 bit length is selected. Bit 2 : Receive Up Code Definition Bit 2 (C2). A Don't Care if a 1 to 7 bit length is selected. Bit 1 : Receive Up Code Definition Bit 1 (C1). A Don't Care if a 1 to 7 bit length is selected. Bit 0 : Receive Up Code Definition Bit 0 (C0). A Don't Care if a 1 to 7 bit length is selected.
Register Name: Register Description: Register Address:
T1RDNCD1 Receive Down Code Definition Register 1 0AEH + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0
Bit # Name Default
7 C7 0
Note: Writing this register resets the detector's integration period. Bit 7 : Receive Down Code Definition Bit 7 (C7). First bit of the repeating pattern. Bit 6 : Receive Down Code Definition Bit 6 (C6). A Don't Care if a 1-bit length is selected. Bit 5 : Receive Down Code Definition Bit 5 (C5). A Don't Care if a 1 or 2 bit length is selected. Bit 4 : Receive Down Code Definition Bit 4 (C4). A Don't Care if a 1 to 3 bit length is selected. Bit 3 : Receive Down Code Definition Bit 3 (C3). A Don't Care if a 1 to 4 bit length is selected. Bit 2 : Receive Down Code Definition Bit 2 (C2). A Don't Care if a 1 to 5 bit length is selected. Bit 1 : Receive Down Code Definition Bit 1 (C1). A Don't Care if a 1 to 6 bit length is selected. Bit 0 : Receive Down Code Definition Bit 0 (C0). A Don't Care if a 1 to 7 bit length is selected.
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
T1RDNCD2 Receive Down Code Definition Register 2 0AFH + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0
Bit # Name Default
7 C7 0
Bit 7 : Receive Down Code Definition Bit 7 (C7). A Don't Care if a 1 to 7 bit length is selected. Bit 6 : Receive Down Code Definition Bit 6 (C6). A Don't Care if a 1 to 7 bit length is selected. Bit 5 : Receive Down Code Definition Bit 5 (C5). A Don't Care if a 1 to 7 bit length is selected. Bit 4 : Receive Down Code Definition Bit 4 (C4). A Don't Care if a 1 to 7 bit length is selected. Bit 3 : Receive Down Code Definition Bit 3 (C3). A Don't Care if a 1 to 7 bit length is selected. Bit 2 : Receive Down Code Definition Bit 2 (C2). A Don't Care if a 1 to 7 bit length is selected. Bit 1 : Receive Down Code Definition Bit 1 (C1). A Don't Care if a 1 to 7 bit length is selected. Bit 0 : Receive Down Code Definition Bit 0 (C0). A Don't Care if a 1 to 7 bit length is selected.
Register Name: Register Description: Register Address:
RRTS1 Receive Real-Time Status Register 1 0B0H + (200h x n): where n = 0 to 7, for Ports 1 to 8 3 RRAI 0 2 RAIS 0 1 RLOS 0 0 RLOF 0
Bit # 7 6 5 4 Name ----Default 0 0 0 0 All bits in this register are real-time (not latched).
Bit 3 : Receive Remote Alarm Indication Condition (RRAI). Set when a remote alarm is received at RTIP and RRING. Bit 2 : Receive Alarm Indication Signal Condition (RAIS). Set when an unframed all one's code is received at RTIP and RRING. Bit 1 : Receive Loss of Signal Condition (RLOS). Set when 192 consecutive zeros have been detected at RTIP and RRING. Bit 0 : Receive Loss of Frame Condition (RLOF). Set when the DS26528 is not synchronized to the received data stream.
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RRTS3 - T1 Mode Receive Real-Time Status Register 3 0B2H + (200h x n): where n = 0 to 7, for Ports 1 to 8 3 LORC 0 2 LSP 0 1 LDN 0 0 LUP 0
Bit # 7 6 5 4 Name ----Default 0 0 0 0 All bits in this register are real-time (not latched).
Bit 3 : Loss of Receive Clock Condition (LORC). Set when the RCLK pin has not transitioned for one channel time. Bit 2 : Spare Code Detected Condition (LSP). Set when the spare code as defined in the RSCD1/2 registers is being received. Bit 1 : Loop Down Code Detected Condition (LDN). Set when the loop down code as defined in the RDNCD1/2 register is being received. Bit 0 : Loop Up Code Detected Condition (LUP). Set when the loop up code as defined in the RUPCD1/2 register is being received.
Register Name: Register Description: Register Address:
RRTS3 - E1 Mode Receive Real-Time Status Register 3 0B2H 3 LORC 0 2 0 1 V52LNK 0 0 RDMA 0
Bit # 7 6 5 4 Name Default 0 0 0 0 Note: All bits in this register are real-time (not latched).
Bit 3 : Loss of Receive Clock Condition (LORC). Set when the RCLK pin has not transitioned for one channel time. Bit 1 : V5.2 Link Detected Condition (V52LNK). Set on detection of a V5.2 link identification signal. (G.965). Bit 0 : Receive Distant MF Alarm Condition (RDMA). Set when bit-6 of time slot 16 in frame 0 has been set for two consecutive multiframes. This alarm is not disabled in the CCS signaling mode.
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RRTS5 Receive Real-Time Status Register 5 (HDLC) 0B4H + (200h x n): where n = 0 to 7, for Ports 1 to 8 4 PS0 0 3 0 2 0 1 RHWM 0 0 RNE 0
Bit # 7 6 5 Name PS2 PS1 Default 0 0 0 All bits in this register are real time.
Bits 6 to 4 : Receive Packet Status (PS0 to PS2). These are real-time bits indicating the status as of the last read of the receive FIFO. PS2 0 0 0 0 1 PS1 0 0 1 1 0 PS0 0 1 0 1 0 PACKET STATUS In Progress: End of message has not yet been reached. Packet OK: Packet ended with correct CRC codeword. CRC Error: A closing flag was detected, preceded by a corrupt CRC codeword. Abort: Packet ended because an abort signal was detected. (7 or more ones in a row). Overrun: HDLC controller terminated reception of packet because receive FIFO is full.
Bit 1 : Receive FIFO Above High Watermark Condition (RHWM). Set when the receive 64-byte FIFO fills beyond the high watermark as defined by the Receive HDLC FIFO Control Register (RHFC). This is a real-time bit. Bit 0 : Receive FIFO Not Empty Condition (RNE). Set when the receive 64-byte FIFO has at least one byte available for a read. This is a real-time bit.
Register Name: Register Description: Register Address:
RHPBA Receive HDLC Packet Bytes Available Register 0B5H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 RPBA6 0 5 RPBA5 0 4 RPBA4 0 3 RPBA3 0 2 RPBA2 0 1 RPBA1 0 0 RPBA0 0
Bit # Name Default
7 MS 0
Bit 7 : Message Status (MS). 0 = Bytes indicated by RPBA0 through RPBA6 are the end of a message. Host must check the HDLC Status register for details. 1 = Bytes indicated by RPBA0 through RPBA6 are the beginning or continuation of a message. The host does not need to check the HDLC Status. The MS bit will return to a value of `1' when the Rx HDLC FIFO is empty. Bits 6 to 0 : Receive FIFO Packet Bytes Available Count (RPBA6 to RPBA0). RPBA0 is the LSB.
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RHF Receive HDLC FIFO Register 0B6H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 RHD6 0 5 RHD5 0 4 RHD4 0 3 RHD3 0 2 RHD2 0 1 RHD1 0 0 RHD0 0
Bit # Name Default
7 RHD7 0
Bit 7 : Receive HDLC Data Bit 7 (RHD7). MSB of a HDLC packet data byte. Bit 6 : Receive HDLC Data Bit 6 (RHD6). Bit 5 : Receive HDLC Data Bit 5 (RHD5). Bit 4 : Receive HDLC Data Bit 4 (RHD4). Bit 3 : Receive HDLC Data Bit 3 (RHD3). Bit 2 : Receive HDLC Data Bit 2 (RHD2). Bit 1 : Receive HDLC Data Bit 1 (RHD1). Bit 0 : Receive HDLC Data Bit 0 (RHD0). LSB of a HDLC packet data byte.
Register Name: Register Description: Register Address:
RBCS1, RBCS2, RBCS3, RBCS4 Receive Blank Channel Select Registers 0C0H, 0C1H, 0C2H, 0C3H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 CH7 CH15 CH23 CH31 0 5 CH6 CH14 CH22 CH30 0 4 CH5 CH13 CH21 CH29 0 3 CH4 CH12 CH20 CH28 0 2 CH3 CH11 CH19 CH27 0 1 CH2 CH10 CH18 CH26 0 0 CH1 CH9 CH17 CH25 0
Bit # Name Name Name Name Default
7 CH8 CH16 CH24 CH32 0
RBCS1 RBCS2 RBCS3 RBCS4
Bit 7 to 0 : Receive Blank Channel Select for Channels 32 to 1 (CH1-32). 0 = do not blank this channel (channel data is available on RSER) 1 = data on RSER is forced to all ones for this channel Note that when two or more sequential channels are chosen to be blanked, the receive slip zone select bit should be set to zero. If the blank channels are distributed (such as 1, 5, 9, 13, 17, 21, 25, 29) then the RSZS bit can be set to one, which may provide a lower occurrence of slips in certain applications.
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
RCBR1, RCBR2, RCBR3, RCBR4 Receive Channel Blocking Registers 0C4H, 0C5H, 0C6H, 0C7H + (200h x n): where n = 0 to 7, for Ports 1 to 8
Bit # Name Name Name Name Default
7 CH8 CH16 CH24 CH32 0
6 CH7 CH15 CH23 CH31 0
5 CH6 CH14 CH22 CH30 0
4 CH5 CH13 CH21 CH29 0
3 CH4 CH12 CH20 CH28 0
2 CH3 CH11 CH19 CH27 0
1 CH2 CH10 CH18 CH26 0
0 CH1 CH9 CH17 CH25 (Fbit) 0
RCBR1 RCBR2 RCBR3 RCBR4
Bits 7 to 0 : Channel Blocking Control Bits for Receive Channels 32 to 1 (CH32 - CH1). 0 = force the RCHBLK pin to remain low during this channel time 1 = force the RCHBLK pin high during this channel time * Note that RCBR4 has two functions: When 2.048MHz backplane mode is selected, this register allows the user to enable the channel blocking signal for any of the 32 possible backplane channels. When 1.544MHz backplane mode is selected, the LSB of this register determines whether or not the RCHBLK signal will pulse high during the F-Bit time. In this mode RCBR4.1 to RCBR4.7 should be set to '0'. RCBR4.0 = 0, do not pulse RCHBLK during the F-Bit RCBR4.0 = 1, pulse RCHBLK during the F-Bit
Register Name: Register Description: Register Address:
RSI1, RSI2, RSI3, RSI4 Receive Signaling Reinsertion Enable Registers 0C8H, 0C9H, 0CAH, 0CBH + (200h x n): where n = 0 to 7, for Ports 1 to 8
Bit # Name Name Name Name Default
7 CH8 CH16 CH24 CH32 0
6 CH7 CH15 CH23 CH31 0
5 CH6 CH14 CH22 CH30 0
4 CH5 CH13 CH21 CH29 0
3 CH4 CH12 CH20 CH28 0
2 CH3 CH11 CH19 CH27 0
1 CH2 CH10 CH18 CH26 0
0 CH1 CH9 CH17 CH25 0
RSI1 RSI2 RSI3 RSI4
Setting any of the CH1 through CH24 bits in the RSI1 through RSI4 registers will cause signaling data to be reinserted for the associated channel. RSI4 is used for 2.048MHz backplane operation.
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Register Name: Register Description: Register Address:
RGCCS1, RGCCS2, RGCCS3, RGCCS4 Receive Gapped Clock Channel Select Registers 0CCH, 0CDH, 0CEH, 0CFH + (200h x n): where n = 0 to 7, for Ports 1 to 8
Bit # Name Name Name Name Default
7 CH8 CH16 CH24 CH32 0
6 CH7 CH15 CH23 CH31 0
5 CH6 CH14 CH22 CH30 0
4 CH5 CH13 CH21 CH29 0
3 CH4 CH12 CH20 CH28 0
2 CH3 CH11 CH19 CH27 0
1 CH2 CH10 CH18 CH26 0
0 CH1 CH9 CH17 CH25 (Fbit) 0
RGCCS1 RGCCS2 RGCCS3 RGCCS4
Bits 7 to 0 : Gapped Clock Channel Select Bits for Receive Channels 32 to 1(CH32 - CH1). 0 = no clock is present on RCHCLK during this channel time 1 = force a clock on RCHCLK during this channel time. The clock will be synchronous with RCLK if the elastic store is disabled, and synchronous with RSYSCLK if the elastic store is enabled. * Note that RGCCS4 has two functions: When 2.048MHz backplane mode is selected, this register allows the user to enable the 'gapped' clock on RCHCLK for any of the 32 possible backplane channels. When 1.544MHz backplane mode is selected, the LSB of this register determines whether or not a clock is generated on RCHCLK during the F-Bit time: RGCCS4.0 = 0, do not generate a clock during the F-Bit RGCCS4.0 = 1, generate a clock during the F-Bit In this mode RGCCS4.1 to RGCCS4.7 should be set to '0'.
Register Name: Register Description: Register Address:
RCICE1, RCICE2, RCICE3, RCICE4 Receive Channel Idle Code Enable Registers 0D0H, 0D1H, 0D2H, 0D3H + (200h x n): where n = 0 to 7, for Ports 1 to 8 (LSB) CH1 CH9 CH17 CH25
(MSB) CH8 CH16 CH24 CH32
CH7 CH15 CH23 CH31
CH6 CH14 CH22 CH30
CH5 CH13 CH21 CH29
CH4 CH12 CH20 CH28
CH3 CH11 CH19 CH27
CH2 CH10 CH18 CH26
RCICE1 RCICE2 RCICE3 RCICE4
Bits 7 to 0 : Receive Channels 1 to 32 Code Insertion Control Bits (CH1 to CH32) 0 = do not insert data from the Idle Code Array into the receive data stream 1 = insert data from the Idle Code Array into the receive data stream
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Register Name: Register Description: Register Address:
RBPCS1, RBPCS2, RBPCS3, RBPCS4 Receive BERT Port Channel Select Registers 0D4H, 0D5H, 0D6H, 0D7H + (200h x n): where n = 0 to 7, for Ports 1 to 8 (LSB) CH1 CH9 CH17 CH25
(MSB) CH8 CH16 CH24 CH32
CH7 CH15 CH23 CH31
CH6 CH14 CH22 CH30
CH5 CH13 CH21 CH29
CH4 CH12 CH20 CH28
CH3 CH11 CH19 CH27
CH2 CH10 CH18 CH26
RBPCS1 RBPCS2 RBPCS3 RBPCS4
Bits 7 to 0 : BERT Port Channel Select Receive Channels 1 to 32(CH1 to CH32) 0 = Do not enable RBP_CLK for the associated channel time, or map the selected channel data out of the receive BERT Port. 1 = Enable RBP_CLK for the associated channel time, and allow mapping of the selected channel data out of the receive BERT Port. Multiple, or all channels may be selected simultaneously.
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10.4.2 Transmit Register Definitions
Register Name: Register Description: Register Address:
THC1 Transmit HDLC Control Register 1 110H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 TEOML 0 5 THR 0 4 THMS 0 3 TFS 0 2 TEOM 0 1 TZSD 0 0 TCRCD 0
Bit # Name Default
7 NOFS 0
Bit 7 : Number Of Flags Select (NOFS). 0 = send one flag between consecutive messages 1 = send two flags between consecutive messages Bit 6 : Transmit End of Message and Loop (TEOML). To loop on a message, should be set to a one just before the last data byte of an HDLC packet is written into the transmit FIFO. The message will repeat until the user clears this bit or a new message is written to the transmit FIFO. If the host clears the bit, the looping message will complete then flags will be transmitted until new message is written to the FIFO. If the host terminates the loop by writing a new message to the FIFO the loop will terminate, one or two flags will be transmitted and the new message will start. If not disabled via TCRCD, the transmitter will automatically append a two-byte CRC code to the end of all messages. Bit 5 : Transmit HDLC Reset (THR). Will reset the transmit HDLC controller and flush the transmit FIFO. An abort followed by 7Eh or FFh flags/idle will be transmitted until a new packet is initiated by writing new data into the FIFO. This is an acknowledged reset, that is, the host need only to set the bit and the DS26528 will clear it once the reset operation is complete. Total time for the reset is less than 250ms. 0 = Normal operation 1 = Reset transmit HDLC controller and flush the transmit FIFO Bit 4 : Transmit HDLC Mapping Select (THMS). 0 = Transmit HDLC assigned to channels 1 = Transmit HDLC assigned to FDL(T1 mode), Sa Bits(E1 mode). This mode must be enabled with TCR2.7. Bit 3 : Transmit Flag/Idle Select (TFS). This bit selects the inter-message fill character after the closing and before the opening flags (7Eh). 0 = 7Eh 1 = FFh Bit 2 : Transmit End of Message (TEOM). Should be set to a one just before the last data byte of an HDLC packet is written into the transmit FIFO at THF. If not disabled via TCRCD, the transmitter will automatically append a two byte CRC code to the end of the message. Bit 1 : Transmit Zero Stuffer Defeat (TZSD). The Zero Stuffer function automatically inserts a zero in the message field (between the flags) after 5 consecutive ones to prevent the emulation of a flag or abort sequence by the data pattern. The receiver automatically removes (de-stuffs) any zero after 5 ones in the message field. 0 = enable the zero stuffer (normal operation) 1 = disable the zero stuffer Bit 0 : Transmit CRC Defeat (TCRCD). A two-byte CRC code is automatically appended to the outbound message. This bit can be used to disable the CRC function. 0 = enable CRC generation (normal operation) 1 = disable CRC generation
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Register Name: Register Description: Register Address:
THBSE Transmit HDLC Bit Suppress 111H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 TBSE7 0 5 TBSE6 0 4 TBSE5 0 3 TBSE4 0 2 TBSE3 0 1 TBSE2 0 0 TBSE1 0
Bit # Name Default
7 TBSE8 0
Bit 7 : Transmit Bit 8 Suppress (TBSE8). MSB of the channel. Set to one to stop this bit from being used. Bit 6 : Transmit Bit 7 Suppress (TBSE7). Set to one to stop this bit from being used. Bit 5 : Transmit Bit 6 Suppress (TBSE6). Set to one to stop this bit from being used. Bit 4 : Transmit Bit 5 Suppress (TBSE5). Set to one to stop this bit from being used Bit 3 : Transmit Bit 4 Suppress (TBSE4). Set to one to stop this bit from being used Bit 2 : Transmit Bit 3 Suppress (TBSE3). Set to one to stop this bit from being used Bit 1 : Transmit Bit 2 Suppress (TBSE2). Set to one to stop this bit from being used Bit 0 : Transmit Bit 1 Suppress (TBSE1). LSB of the channel. Set to one to stop this bit from being used.
Register Name: Register Description: Register Address:
THC2 Transmit HDLC Control Register 2 113H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 SBOC 0 5
THCEN
Bit # Name Default
7 TABT 0
0
4 THCS4 0
3 THCS3 0
2 THCS2 0
1 THCS1 0
0 THCS0 0
Bit 7 : Transmit Abort (TABT). A 0-to-1 transition will cause the FIFO contents to be dumped and one FEh abort to be sent followed by 7Eh or FFh flags/idle until a new packet is initiated by writing new data into the FIFO. Must be cleared and set again for a subsequent abort to be sent. Bit 6 : Send BOC (SBOC). T1 Mode Only. Set = 1 to transmit the BOC code placed in bits 0 to 5 of the TBOC register. Bit 5 : Transmit HDLC Controller Enable (THCEN). 0 = Transmit HDLC Controller is not enabled 1 = Transmit HDLC Controller is enabled Bits 4 to 0 : Transmit HDLC Channel Select (THCS4-0). Determines which DSO channel will carry the HDLC message if enabled. Changes to this value are acknowledged only upon a transmit HDLC controller reset (THR at THC1.5).
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Register Name: Register Description: Register Address:
E1TSACR E1 Transmit Sa Bit Control Register 114h + (200h * n) : where n = 0 to 7, for Ports 1 to 8 6 SiNAF 0 5 RA 0 4 Sa4 0 3 Sa5 0 2 Sa6 0 1 Sa7 0 0 Sa8 0
Bit # Name Default
7 SiAF 0
Bit 7 : International Bit in Align Frame Insertion Control Bit (SiAF). 0 = do not insert data from the TSiAF register into the transmit data stream 1 = insert data from the TSiAF register into the transmit data stream Bit 6 : International Bit in Non-Align Frame Insertion Control Bit (SiNAF). 0 = do not insert data from the TSiNAF register into the transmit data stream 1 = insert data from the TSiNAF register into the transmit data stream Bit 5 : Remote Alarm Insertion Control Bit (RA). 0 = do not insert data from the TRA register into the transmit data stream 1 = insert data from the TRA register into the transmit data stream Bit 4 : Additional Bit 4 Insertion Control Bit (Sa4). 0 = do not insert data from the TSa4 register into the transmit data stream 1 = insert data from the TSa4 register into the transmit data stream Bit 3 : Additional Bit 5 Insertion Control Bit (Sa5). 0 = do not insert data from the TSa5 register into the transmit data stream 1 = insert data from the TSa5 register into the transmit data stream Bit 2 : Additional Bit 6 Insertion Control Bit (Sa6). 0 = do not insert data from the TSa6 register into the transmit data stream 1 = insert data from the TSa6 register into the transmit data stream Bit 1 : Additional Bit 7 Insertion Control Bit (Sa7). 0 = do not insert data from the TSa7 register into the transmit data stream 1 = insert data from the TSa7 register into the transmit data stream Bit 0 : Additional Bit 8 Insertion Control Bit (Sa8). 0 = do not insert data from the TSa8 register into the transmit data stream 1 = insert data from the TSa8 register into the transmit data stream
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DS26528 Octal T1/E1/J1 Transceiver Register Name: Register Description: Register Address: (MSB) CH8 CH16 CH24 CH32 SSIE1, SSIE2, SSIE3, SSIE4 Software Signaling Insertion Enable Registers 118H, 119H, 11AH, 11BH + (200h x n): where n = 0 to 7, for Ports 1 to 8 (LSB) CH1 CH9 CH17 CH25
CH7 CH15 CH23 CH31
CH6 CH14 CH22 CH30
CH5 CH13 CH21 CH29
CH4 CH12 CH20 CH28
CH3 CH11 CH19 CH27
CH2 CH10 CH18 CH26
SSIE1 SSIE2 SSIE3 SSIE4
Bits 7 to 0 : Software Signaling Insertion Enable for Channels 1 to 32 (SSIEx). These bits determine which channels are to have signaling inserted form the Transmit Signaling registers. 0 = do not source signaling data from the TS registers for this channel 1 = source signaling data from the TS registers for this channel
Register Name: Register Description: Register Address:
TIDR1 to TIDR32 Transmit Idle Code Definition Registers 1 to 32 120H to 13FH + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0
Bit # Name Default
7 C7 0
Bits 7 to 0 : Per-Channel Idle Code Bits (C7 to C0). C0 is the LSB of the Code (this bit is transmitted last). Address 120H is for channel 1, address 13FH is for channel 32.
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Register Name: Register Description: Register Address:
TS1 to TS16 Transmit Signaling Registers 140H - 14FH + (200h x n): where n = 0 to 7, for Ports 1 to 8 (LSB) CH13-D CH14-D CH15-D CH16-D CH17-D CH18-D CH19-D CH20-D CH21-D CH22-D CH23-D CH24-D
T1 Mode: (MSB) CH1-A CH1-B CH1-C CH1-D CH13-A CH13-B CH2-A CH2-B CH2-C CH2-D CH14-A CH14-B CH3-A CH3-B CH3-C CH3-D CH15-A CH15-B CH4-A CH4-B CH4-C CH4-D CH16-A CH16-B CH5-A CH5-B CH5-C CH5-D CH17-A CH17-B CH6-A CH6-B CH6-C CH6-D CH18-A CH18-B CH7-A CH7-B CH7-C CH7-D CH19-A CH19-B CH8-A CH8-B CH8-C CH8-D CH20-A CH20-B CH9-A CH9-B CH9-C CH9-D CH21-A CH21-B CH10-A CH10-B CH10-C CH10-D CH22-A CH22-B CH11-A CH11-B CH11-C CH11-D CH23-A CH23-B CH12-A CH12-B CH12-C CH12-D CH24-A CH24-B Note: In D4 framing mode, the C and D bits are not used. E1 Mode: (MSB) 0 CH1-A CH2-A CH3-A CH4-A CH5-A CH6-A CH7-A CH8-A CH9-A CH10-A CH11-A CH12-A CH13-A CH14-A CH15-A
CH13-C CH14-C CH15-C CH16-C CH17-C CH18-C CH19-C CH20-C CH21-C CH22-C CH23-C CH24-C
TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12
0 CH1-B CH2-B CH3-B CH4-B CH5-B CH6-B CH7-B CH8-B CH9-B CH10-B CH11-B CH12-B CH13-B CH14-B CH15-B
0 CH1-C CH2-C CH3-C CH4-C CH5-C CH6-C CH7-C CH8-C CH9-C CH10-C CH11-C CH12-C CH13-C CH14-C CH15-C
0 CH1-D CH2-D CH3-D CH4-D CH5-D CH6-D CH7-D CH8-D CH9-D CH10-D CH11-D CH12-D CH13-D CH14-D CH15-D
X CH16-A CH17-A CH18-A CH19-A CH20-A CH21-A CH22-A CH23-A CH24-A CH25-A CH26-A CH27-A CH28-A CH29-A CH30-A
Y CH16-B CH17-B CH18-B CH19-B CH20-B CH21-B CH22-B CH23-B CH24-B CH25-B CH26-B CH27-B CH28-B CH29-B CH30-B
X CH16-C CH17-C CH18-C CH19-C CH20-C CH21-C CH22-C CH23-C CH24-C CH25-C CH26-C CH27-C CH28-C CH29-C CH30-C
(LSB) X CH16-D CH17-D CH18-D CH19-D CH20-D CH21-D CH22-D CH23-D CH24-D CH25-D CH26-D CH27-D CH28-D CH29-D CH30-D
TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15 TS16
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Register Name: Register Description: Register Address:
TCICE1, TCICE2, TCICE3, TCICE4 Transmit Channel Idle Code Enable Registers 150H, 151H, 152H, 153H + (200h x n): where n = 0 to 7, for Ports 1 to 8 (LSB) CH1 CH9 CH17 CH25
(MSB) CH8 CH16 CH24 CH32
CH7 CH15 CH23 CH31
CH6 CH14 CH22 CH30
CH5 CH13 CH21 CH29
CH4 CH12 CH20 CH28
CH3 CH11 CH19 CH27
CH2 CH10 CH18 CH26
TCICE1 TCICE2 TCICE3 TCICE4
The Transmit Channel Idle Code Enable Registers (TCICE1:2:3:4) are used to determine which of the 24 T1 channels (or 32 E1 Channels) from the backplane should be overwritten with the code placed in the Transmit Idle Code Definition Register. Bits 7 to 0 : Transmit Channels 1 to 32 Code Insertion Control Bits (CH1 to CH32) 0 = do not insert data from the Idle Code Array into the transmit data stream 1 = insert data from the Idle Code Array into the transmit data stream
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
TFRID Transmit Firmware Revision ID Register 161H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 FR6 0 5 FR5 0 4 FR4 0 3 FR3 0 2 FR2 0 1 FR1 0 0 FR0 0
Bit # Name Default
7 FR7 0
Bits 7 to 0 : Firmware Revision (FR0-FR7). This read-only register reports the transmitter firmware revision.
Register Name: Register Description: Register Address:
T1TFDL Transmit FDL Register 162H + (200h x n): where n = 0 to 7, for Ports 1 to 8 2 CH3 0 1 CH2 0 0 CH1 0
Bit # 7 6 5 4 3 Name CH8 CH7 CH6 CH5 CH4 Default 0 0 0 0 0 [also used to insert Fs framing pattern in D4 framing mode]
The Transmit FDL Register (TFDL) contains the Facility Data Link (FDL) information that is to be inserted on a byte basis into the outgoing T1 data stream. The LSB is transmitted first. In D4 mode, only the lower six bits are used. Bit 7 : Transmit FDL Bit 7 (TFDL7). MSB of the Transmit FDL Code. Bit 6 : Transmit FDL Bit 6 (TFDL6). Bit 5 : Transmit FDL Bit 5 (TFDL5). Bit 4 : Transmit FDL Bit 4 (TFDL4). Bit 3 : Transmit FDL Bit 3 (TFDL3). Bit 2 : Transmit FDL Bit 2 (TFDL2). Bit 1 : Transmit FDL Bit 1 (TFDL1). Bit 0 : Transmit FDL Bit 0 (TFDL0). LSB of the Transmit FDL Code.
Register Name: Register Description: Register Address:
T1TBOC Transmit BOC Register 163H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 0 5 TBOC5 0 4 TBOC4 0 3 TBOC3 0 2 TBOC2 0 1 TBOC1 0 0 TBOC0 0
Bit # Name Default
7 0
Bit 5 : Transmit BOC Bit 5 (TBOC5). MSB of the Transmit BOC Code. Bit 4 : Transmit BOC Bit 4 (TBOC4). Bit 3 : Transmit BOC Bit 3 (TBOC3). Bit 2 : Transmit BOC Bit 2 (TBOC2). Bit 1 : Transmit BOC Bit 1 (TBOC1). Bit 0 : Transmit BOC Bit 0 (TBOC0). LSB of the Transmit BOC Code.
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Register Name: Register Description: Register Address:
T1TSLC1, T1TSLC2, T1TSLC3 Transmit SLC96 Data Link Registers 164H, 165H, 166H + (200h x n): where n = 0 to 7, for Ports 1 to 8 (LSB) C1 C9 M3
(MSB) C8 M2 S=1
C7 M1 S4
C6 S=0 S3
C5 S=1 S2
C4 S=0 S1
C3 C11 A2
C2 C10 A1
T1TSLC1 T1TSLC2 T1TSLC3
Register Name: Register Description: Register Address:
E1TAF Transmit Align Frame Register 164H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 0 0 5 0 0 4 1 1 3 1 1 2 0 0 1 1 1 0 1 1
Bit # Name Default
7 Si 0
Bit 7 : International Bit (Si). Bit 6 : Frame Alignment Signal Bit (0). Bit 5 : Frame Alignment Signal Bit (0). Bit 4 : Frame Alignment Signal Bit (1). Bit 3 : Frame Alignment Signal Bit (1). Bit 2 : Frame Alignment Signal Bit (0). Bit 1 : Frame Alignment Signal Bit (1). Bit 0 : Frame Alignment Signal Bit (1).
Register Name: Register Description: Register Address:
E1TNAF Transmit Non-Align Frame Register 165H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 1 1 5 A 0 4 Sa4 0 3 Sa5 0 2 Sa6 0 1 Sa7 0 0 Sa8 0
Bit # Name Default
7 Si 0
Bit 7 : International Bit (Si). Bit 6 : Frame Non-Alignment Signal Bit (1). Bit 5 : Remote Alarm (Used to Transmit the Alarm (A). Bit 4 : Additional Bit 4 (Sa4). Bit 3 : Additional Bit 5 (Sa5). Bit 2 : Additional Bit 6 (Sa6). Bit 1 : Additional Bit 7 (Sa7). Bit 0 : Additional Bit 8 (Sa8).
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
E1TSiAF Transmit Si Bits of the Align Frame 166H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 TSiF12 0 5 TSiF10 0 4 TSiF8 0 3 TSiF6 0 2 TSiF4 0 1 TSiF2 0 0 TSiF0 0
Bit # Name Default
7 TSiF14 0
Bit 7 : Si Bit of Frame 14 (TSiF14). Bit 6 : Si Bit of Frame 12 (TSiF12). Bit 5 : Si Bit of Frame 10 (TSiF10). Bit 4 : Si Bit of Frame 8 (TSiF8). Bit 3 : Si Bit of Frame 6 (TSiF6). Bit 2 : Si Bit of Frame 4 (TSiF4). Bit 1 : Si Bit of Frame 2 (TSiF2). Bit 0 : Si Bit of Frame 0 (TSiF0).
Register Name: Register Description: Register Address:
E1TSiNAF Transmit Si Bits of the Non-Align Frame 167H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 TSiF13 0 5 TSiF11 0 4 TSiF9 0 3 TSiF7 0 2 TSiF5 0 1 TSiF3 0 0 TSiF1 0
Bit # Name Default
7 TSiF15 0
Bit 7 : Si Bit of Frame 15 (TSiF15). Bit 6 : Si Bit of Frame 13 (TSiF13). Bit 5 : Si Bit of Frame 11 (TSiF11). Bit 4 : Si Bit of Frame 9 (TSiF9). Bit 3 : Si Bit of Frame 7 (TSiF7). Bit 2 : Si Bit of Frame 5 (TSiF5). Bit 1 : Si Bit of Frame 3 (TSiF3). Bit 0 : Si Bit of Frame 1 (TSiF1).
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
E1TRA Transmit Remote Alarm 168H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 TRAF13 0 5 TRAF11 0 4 TRAF9 0 3 TRAF7 0 2 TRAF5 0 1 TRAF3 0 0 TRAF1 0
Bit # Name Default
7 TRAF15 0
Bit 7 : Remote Alarm Bit of Frame 15 (TRAF15). Bit 6 : Remote Alarm Bit of Frame 13 (TRAF13). Bit 5 : Remote Alarm Bit of Frame 11 (TRAF11). Bit 4 : Remote Alarm Bit of Frame 9 (TRAF9). Bit 3 : Remote Alarm Bit of Frame 7 (TRAF7). Bit 2 : Remote Alarm Bit of Frame 5 (TRAF5). Bit 1 : Remote Alarm Bit of Frame 3 (TRAF3). Bit 0 : Remote Alarm Bit of Frame 1 (TRAF1).
Register Name: Register Description: Register Address:
E1TSa4 Transmit Sa4 Bits 169H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 TSa4F13 0 5 TSa4F11 0 4 TSa4F9 0 3 TSa4F7 0 2 TSa4F5 0 1 TSa4F3 0 0 TSa4F1 0
Bit # Name Default
7 TSa4F15 0
Bit 7 : Sa4 Bit of Frame 15 (TSa4F15). Bit 6 : Sa4 Bit of Frame 13 (TSa4F13). Bit 5 : Sa4 Bit of Frame 11 (TSa4F11). Bit 4 : Sa4 Bit of Frame 9 (TSa4F9). Bit 3 : Sa4 Bit of Frame 7 (TSa4F7). Bit 2 : Sa4 Bit of Frame 5 (TSa4F5). Bit 1 : Sa4 Bit of Frame 3 (TSa4F3). Bit 0 : Sa4 Bit of Frame 1 (TSa4F1).
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Register Name: Register Description: Register Address:
E1TSa5 Transmitted Sa5 Bits 16AH + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 TSa5F13 0 5 TSa5F11 0 4 TSa5F9 0 3 TSa5F7 0 2 TSa5F5 0 1 TSa5F3 0 0 TSa5F1 0
Bit # Name Default
7 TSa5F15 0
Bit 7 : Sa5 Bit of Frame 15 (TSa5F15). Bit 6 : Sa5 Bit of Frame 13 (TSa5F13). Bit 5 : Sa5 Bit of Frame 11 (TSa5F11). Bit 4 : Sa5 Bit of Frame 9 (TSa5F9). Bit 3 : Sa5 Bit of Frame 7 (TSa5F7). Bit 2 : Sa5 Bit of Frame 5 (TSa5F5). Bit 1 : Sa5 Bit of Frame 3 (TSa5F3). Bit 0 : Sa5 Bit of Frame 1 (TSa5F1).
Register Name: Register Description: Register Address:
E1TSa6 Transmit Sa6 Bits 16BH + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 TSa6F13 0 5 TSa6F11 0 4 TSa6F9 0 3 TSa6F7 0 2 TSa6F5 0 1 TSa6F3 0 0 TSa6F1 0
Bit # Name Default
7 TSa6F15 0
Bit 7 : Sa6 Bit of Frame 15 (TSa6F15). Bit 6 : Sa6 Bit of Frame 13 (TSa6F13). Bit 5 : Sa6 Bit of Frame 11 (TSa6F11). Bit 4 : Sa6 Bit of Frame 9 (TSa6F9). Bit 3 : Sa6 Bit of Frame 7 (TSa6F7). Bit 2 : Sa6 Bit of Frame 5 (TSa6F5). Bit 1 : Sa6 Bit of Frame 3 (TSa6F3). Bit 0 : Sa6 Bit of Frame 1 (TSa6F1).
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
E1TSa7 Transmit Sa7 Bits 16CH + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 TSa7F13 0 5 TSa7F11 0 4 TSa7F9 0 3 TSa7F7 0 2 TSa7F5 0 1 TSa7F3 0 0 TSa7F1 0
Bit # Name Default
7 TSa7F15 0
Bit 7 : Sa7 Bit of Frame 15 (TSa4F15). Bit 6 : Sa7 Bit of Frame 13 (TSa7F13). Bit 5 : Sa7 Bit of Frame 11 (TSa7F11). Bit 4 : Sa7 Bit of Frame 9 (TSa7F9). Bit 3 : Sa7 Bit of Frame 7 (TSa7F7). Bit 2 : Sa7 Bit of Frame 5 (TSa7F5). Bit 1 : Sa7 Bit of Frame 3 (TSa7F3). Bit 0 : Sa7 Bit of Frame 1 (TSa7F1).
Register Name: Register Description: Register Address:
E1TSa8 Transmit Sa8 Bits 16DH + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 TSa8F13 0 5 TSa8F11 0 4 TSa8F9 0 3 TSa8F7 0 2 TSa8F5 0 1 TSa8F3 0 0 TSa8F1 0
Bit # Name Default
7 TSa8F15 0
Bit 7 : Sa8 Bit of Frame 15 (TSa8F15). Bit 6 : Sa8 Bit of Frame 13 (TSa8F13). Bit 5 : Sa8 Bit of Frame 11 (TSa8F11). Bit 4 : Sa8 Bit of Frame 9 (TSa8F9). Bit 3 : Sa8 Bit of Frame 7 (TSa8F7). Bit 2 : Sa8 Bit of Frame 5 (TSa8F5). Bit 1 : Sa8 Bit of Frame 3 (TSa8F3). Bit 0 : Sa8 Bit of Frame 1 (TSa8F1).
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Register Name: Register Description: Register Address:
TMMR Transmit Master Mode Register 180H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 INIT_DONE 0 5 0 4 0 3 0 2 0 1 SFTRST 0 0 T1/E1 0
Bit # Name Default
7 FRM_EN 0
Bit 7 : Framer Enable (FRM_EN). This bit must be set to the desired state before writing INIT_DONE. 0 = Framer disabled - held in low-power state 1 = Framer enabled - all features active Bit 6 : Initialization Done (INIT_DONE). The user must set this bit once he has written the configuration registers. The host is required to write or clear all device registers prior to setting this bit. Once INIT_DONE is set, the DS26528 will check the FRM_EN bit and, if enabled will begin operation based on the initial configuration. Bit 1 : Soft Reset (SFTRST). Level sensitive `soft' reset. Should be taken high then low to reset the transceiver. 0 = Normal operation 1 = Reset the transceiver. Bit 0 : Transmitter T1/E1 Mode Select (T1/E1). Sets operating mode for transmitter only! This bit must be written with the desired value prior to setting INIT_DONE. 0 = T1 operation 1 = E1 operation
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
TCR1 - T1 Mode Transmit Control Register 1 181H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 TFPT 0 5 TCPT 0 4 TSSE 0 3 GB7S 0 2 TB8ZS 0 1 TAIS 0 0 TRAI 0
Bit # Name Default
7 TJC 0
Bit 7 : Transmit Japanese CRC6 Enable (TJC). 0 = use ANSI/AT&T:ITU CRC6 calculation (normal operation) 1 = use Japanese standard JT-G704 CRC6 calculation Bit 6 : Transmit F-Bit Pass Through (TFPT). 0 = F bits sourced internally 1 = F bits sampled at TSER Bit 5 : Transmit CRC Pass Through (TCPT). 0 = source CRC6 bits internally 1 = CRC6 bits sampled at TSER during F-bit time Bit 4 : Transmit Software Signaling Enable (TSSE). This function is enabled by TB7ZS (TCR2.0). 0 = do not source signaling data from the TSx registers regardless of the SSIEx registers. The SSIEx registers still define which channels are to have B7 stuffing performed. 1 = source signaling data as enabled by the SSIEx registers. Bit 3 : Global Bit 7 Stuffing (GB7S). This function is enabled by TB7ZS (TCR2.0). 0 = allow the SSIEx registers to determine which channels containing all zeros are to be Bit 7 stuffed 1 = force Bit 7 stuffing in all zero byte channels of that port, regardless of how the SSIEx registers are programmed Bit 2 : Transmit B8ZS Enable (TB8ZS). 0 = B8ZS disabled 1 = B8ZS enabled Bit 1 : Transmit Alarm Indication Signal (TAIS). 0 = transmit data normally 1 = transmit an unframed all one's code at TTIP and TRING Bit 0 : Transmit Remote Alarm Indication (TRAI). 0 = do not transmit Remote Alarm 1 = transmit Remote Alarm
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
TCR1 - E1 Mode Transmit Control Register 1 181H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 T16S 0 5 TG802 0 4 TSiS 0 3 TSA1 0 2 THDB3 0 1 TAIS 0 0 TCRC4 0
Bit # Name Default
7 TTPT 0
Bit 7 : Transmit Time Slot 0 Pass Through (TTPT). 0 = FAS bits/Sa bits/Remote Alarm sourced internally from the TAF and TNAF registers 1 = FAS bits/Sa bits/Remote Alarm sourced from TSER Bit 6 : Transmit Time Slot 16 Data Select (T16S). See Section 9.9.4 on Software Signaling. 0 = time slot 16 determined by the SSIEx and THSCS registers 1 = source time slot 16 from TS1 to TS16 registers Bit 5 : Transmit G.802 Enable (TG802). See Section 11.4. 0 = do not force TCHBLK high during bit 1 of time slot 26 1 = force TCHBLK high during bit 1 of time slot 26 Bit 4 : Transmit International Bit Select (TSiS). 0 = sample Si bits at TSER pin 1 = source Si bits from TAF and TNAF registers (in this mode, TCR1.7 must be set to 0) Bit 3 : Transmit Signaling All Ones (TSA1). 0 = normal operation 1 = force time slot 16 in every frame to all ones Bit 2 : Transmit HDB3 Enable (THDB3). 0 = HDB3 disabled 1 = HDB3 enabled Bit 1 : Transmit AIS (TAIS). 0 = transmit data normally 1 = transmit an unframed all-ones code at TTIP and TRING Bit 0 : Transmit CRC4 Enable (TCRC4). 0 = CRC4 disabled 1 = CRC4 enabled
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
TCR2 - T1 Mode Transmit Control Register 2 182H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 TSLC96 0 5 0 4 FBCT2 0 3 FBCT1 0 2 TD4RM 0 1 PDE 0 0 TB7ZS 0
Bit # Name Default
7 TFDLS 0
Bit 7 : TFDL Register Select (TFDLS). 0 = source FDL or Fs bits from the internal TFDL register or the SLC-96 data formatter (TCR2.6) 1 = source FDL or Fs bits from the internal HDLC controller or the TLINK pin Bit 6 : Transmit SLC-96 (TSLC96). Set this bit to a one in SLC-96 framing applications. Must be set to source the SLC-96 alignment pattern and data from the TSLC1-3 registers. See Section 9.9.4.3 for details. 0 = SLC-96 insertion disabled 1 = SLC-96 insertion enabled Bit 4 : F Bit Corruption Type 2. (FBCT2). Setting this bit high enables the corruption of one Ft (D4 framing mode) or FPS (ESF framing mode) bit in every 128 Ft or FPS bits as long as the bit remains set. Bit 3 : F Bit Corruption Type 1. (FBCT1). A low-to-high transition of this bit causes the next three consecutive Ft (D4 framing mode) or FPS (ESF framing mode) bits to be corrupted causing the remote end to experience a loss of synchronization. Bit 2 : Transmit D4 RAI Select (TD4RM). 0 = zeros in bit 2 of all channels 1 = a one in the S-bit position of frame 12 Bit 1 : Pulse Density Enforcer Enable (PDE). The framer always examines both the transmit and receive data streams for violations of the following rules which are required by ANSI T1.403: no more than 15 consecutive zeros and at least N ones in each and every time window of 8 x (N +1) bits where N = 1 through 23. Violations for the transmit and receive data streams are reported in the TLS1.3 and RLS2.7 bits respectively. When this bit is set to one, the DS26528 will force the transmitted stream to meet this requirement no matter the content of the transmitted stream. When running B8ZS, this bit should be set to zero since B8ZS encoded data streams cannot violate the pulse density requirements. 0 = disable transmit pulse density enforcer 1 = enable transmit pulse density enforcer Bit 0 : Transmit Side Bit 7 Zero Suppression Enable (TB7ZS). 0 = no stuffing occurs 1 = force bit 7 to a one as determined by the GB7S bit at TCR1.3
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
TCR2 - E1 Mode Transmit Control Register 2 182H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 AAIS 0 5 ARA 0 4 Sa4S 0 3 Sa5S 0 2 Sa6S 0 1 Sa7S 0 0 Sa8S 0
Bit # Name Default
7 AEBE 0
Bit 7 : Automatic E-Bit Enable (AEBE). 0 = E-bits not automatically set in the transmit direction 1 = E-bits automatically set in the transmit direction Bit 6 : Automatic AIS Generation (AAIS). 0 = disabled 1 = enabled Bit 5 : Automatic Remote Alarm Generation (ARA). 0 = disabled 1 = enabled Bit 4 : Sa4 Bit Select (Sa4S). Set to one to source the Sa4 bit from the TLINK pin; set to zero to not source the Sa4 bit. Bit 3 : Sa5 Bit Select (Sa5S). Set to one to source the Sa5 bit from the TLINK pin; set to zero to not source the Sa5 bit. Bit 2 : Sa6 Bit Select (Sa6S). Set to one to source the Sa6 bit from the TLINK pin; set to zero to not source the Sa6 bit Bit 1 : Sa7 Bit Select (Sa7S). Set to one to source the Sa7 bit from the TLINK pin; set to zero to not source the Sa7 bit. Bit 0 : Sa8 Bit Select (Sa8S). Set to one to source the Sa8 bit from the TLINK pin; set to zero to not source the Sa8 bit.
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
TCR3 Transmit Control Register 3 183H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 ODM 0 5 TCSS1 0 4 TCSS0 0 3 MFRS 0 2 TFM 0 1 IBPV 0 0 TLOOP 0
Bit # Name Default
7 ODF 0
Bit 7 : Output Data Format (ODF). 0 = bipolar data at TTIP and TRING 1 = NRZ data at TTIP; TRING = 0 Bit 6 : Output Data Mode (ODM). 0 = pulses at TTIP and TRING are one full TCLK period wide 1 = pulses at TTIP and TRING are 1/2 TCLK period wide Bits 5, 4 : Transmit Clock Source Select 1, 0 (TCSS1/0). TCSS1 0 0 1 1 TCSS0 0 1 0 1 Transmit Clock Source The TCLK pin is always the source of Transmit Clock. Switch to the clock present at RCLK when the signal at the TCLK pin fails to transition after 1 channel time. Reserved Use the signal present at RCLK as the Transmit Clock. The TCLK pin is ignored.
Bit 3 : Multiframe Reference Select (MFRS). This bit selects the source for the transmit formatter multiframe boundary. 0 = Normal Operation. Transmit multiframe boundary is determined by 'line-side' counters referenced to TSYNC when TSYNC is an input. Free-running when TSYNC is an output. 1 = Pass-Forward Operation. Tx multiframe boundary determined by 'system-side' counters referenced to TSSYNCIO( input mode3), which is then 'passed forward' to the line side clock domain. This mode can only be used when the transmit elastic store is enabled with a synchronous backplane (ie: no frame slips allowed). This mode must be used to allow Tx hardware signaling insertion while the Tx elastic store is enabled. Bit 2 : Transmit Frame Mode Select (TFM). T1 Mode Only 0 = ESF framing mode 1 = D4 framing mode Bit 1 : Insert BPV (IBPV). A 0-to-1 transition on this bit will cause a single BiPolar Violation (BPV) to be inserted into the transmit data stream. Once this bit has been toggled from a 0 to a 1, the device waits for the next occurrence of three consecutive ones to insert the BPV. This bit must be cleared and set again for a subsequent error to be inserted. Bit 0 (T1 Mode): Transmit Loop Code Enable (TLOOP). See Section 9.9.15 for details. 0 = transmit data normally 1 = replace normal transmitted data with repeating code as defined in registers TCD1 and TCD2 Bit 0 (E1 Mode) : CRC-4 Recalculate (CRC4R). 0 = transmit CRC-4 generation and insertion operates in normal mode 1 = transmit CRC-4 generation operates according to G.706 Intermediate Path Recalculation method.
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
TIOCR Transmit I/O Configuration Register 184H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6
TSYNCINV
Bit # Name Default
7
TCLKINV
5
TSSYNCINV
4
TSCLKM
3
TSSM
2
TSIO
1
TSDW
0
TSM
0
0
0
0
0
0
0
0
Bit 7 : TCLK Invert (TCLKINV). 0 = No inversion 1 = Invert Bit 6 : TSYNC Invert (TSYNCINV). 0 = No inversion 1 = Invert Bit 5 : TSSYNCIO(Input Mode Only) Invert (TSSYNCINV). 0 = No inversion 1 = Invert Bit 4 : TSYSCLK Mode Select (TSCLKM). 0 = if TSYSCLK is 1.544MHz 1 = if TSYSCLK is 2.048/4.096/8.192MHz or IBO enabled (see Section 9.8.2 for details on IBO function) Bit 3 : TSSYNCIO Mode Select (TSSM). Selects frame or multiframe mode for the TSSYNCIO pin. 0 = frame mode 1 = multiframe mode Bit 2 : TSYNC I/O Select (TSIO). 0 = TSYNC is an input 1 = TSYNC is an output Bit 1 : TSYNC Double-Wide (TSDW). (Note: this bit must be set to zero when TSM = 1 or when TSIO = 0) 0 = do not pulse double-wide in signaling frames 1 = do pulse double-wide in signaling frames Bit 0 : TSYNC Mode Select (TSM). Selects frame or multiframe mode for the TSYNC pin. 0 = frame mode 1 = multiframe mode
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
TESCR Transmit Elastic Store Control Register 185H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6
TGCLKEN
Bit # Name Default
7
TDATFMT
5
--
4
TSZS
3
TESALGN
2
TESR
1
TESMDM
0
TESE
0
0
0
0
0
0
0
0
Bit 7 : Transmit Channel Data Format (TDATFMT). 0 = 64kBps (data contained in all 8 bits) 1 = 56kBps (data contained in 7 out of the 8 bits) Bit 6 : Transmit Gapped Clock Enable (TGPCKEN). 0 = TCHCLK functions normally 1 = Enable gapped bit clock output on TCHCLK Note: Bits 6 and 7 are used for fractional backplane support. See Section 9.8.5. Bit 5 : Reserved, must be set to zero for proper operation. Bit 4 : Transmit Slip Zone Select (TSZS). This bit determines the minimum distance allowed between the elastic store read and write pointers before forcing a controlled slip. This bit is only applies during T1 to E1 or E1 to T1 conversion applications. 0 = force a slip at 9 bytes or less of separation (used for clustered blank channels) 1 = force a slip at 2 bytes or less of separation (used for distributed blank channels) Bit 3 : Transmit Elastic Store Align (TESALGN). Setting this bit from a zero to a one will force the transmit elastic store's write/read pointers to a minimum separation of half a frame. No action will be taken if the pointer separation is already greater or equal to half a frame. If pointer separation is less than half a frame, the command will be executed and the data will be disrupted. Should be toggled after TSYSCLK has been applied and is stable. Must be cleared and set again for a subsequent align. Bit 2 : Transmit Elastic Store Reset (TESR). Setting this bit from a zero to a one will force the read pointer into the same frame that the write pointer is exiting, minimizing the delay through the elastic store. If this command should place the pointers within the slip zone (see bit 4), then an immediate slip will occur and the pointers will move back to opposite frames. Should be toggled after TSYSCLK has been applied and is stable. Do not leave this bit set HIGH. Bit 1 : Transmit Elastic Store Minimum Delay Mode (TESMDM). 0 = elastic stores operate at full two frame depth 1 = elastic stores operate at 32-bit depth Bit 0 : Transmit Elastic Store Enable (TESE). 0 = elastic store is bypassed 1 = elastic store is enabled
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
TCR4 -- T1 Mode Only Transmit Control Register 4 186H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 0 5 0 4 0 3 TRAIM 0 2 TAISM 0 1 TC1 0 0 TC0 0
Bit # Name Default
7 0
Bits 3 : Transmit RAI Mode (TRAIM). Determines the pattern sent when TRAI (TCR1.0) is activated in ESF frame mode only. 0 = transmit normal RAI upon activation with TCR1.0 1 = transmit RAI-CI (T1.403) upon activation with TCR1.0 Bits 2 : Transmit AIS Mode (TAISM). Determines the pattern sent when TAIS (TCR1.1) is activated. 0 = transmit normal AIS (unframed all ones) upon activation with TCR1.1 1 = transmit AIS-CI (T1.403) upon activation with TCR1.1 Bits 1, 0 : Transmit Code Length Definition Bits (TC[1:0]). TC1 0 0 1 1 TC0 0 1 0 1 Length Selected 5 bits 6 bits : 3 bits 7 bits 16 bits : 8 bits : 4 bits : 2 bits : 1 bit
Register Name: Register Description: Register Address:
THFC Transmit HDLC FIFO Control Register 187H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 0 5 0 4 0 3 0 2 0 1 TFLWM1 0 0 TFLWM2 0
Bit # Name Default
7 0
Bits 1, 0 : Transmit HDLC FIFO Low Watermark Select (TFLWM[1:0]). TFLWM1 0 0 1 1 TFLWM0 0 1 0 1 Transmit FIFO Watermark 4 bytes 16 bytes 32 bytes 48 bytes
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
TIBOC Transmit Interleave Bus Operation Control Register 188H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 IBS1 0 5 IBS0 0 4 IBOSEL 0 3 IBOEN 0 2 DA2 0 1 DA1 0 0 DA0 0
Bit # Name Default
7 0
Bit 7 : Unused, must be set to zero for proper operation. Bits 6, 5 : IBO Bus Size (IBS[1:0]). Indicates how many devices on the bus. IBS1 0 0 1 1 IBS0 0 1 0 1 Bus Size 2 Devices on bus 4 Devices on bus 8 Devices on bus Reserved for future use
Bit 4 : Interleave Bus Operation Select (IBOSEL). This bit selects channel or frame interleave mode. 0 = Channel Interleave 1 = Frame Interleave Bit 3 : Interleave Bus Operation Enable (IBOEN). 0 = Interleave Bus Operation disabled. 1 = Interleave Bus Operation enabled. Bits 2 to 0 : Device Assignment bits (DA[2:0]). DA2 0 0 0 0 1 1 1 1 DA1 0 0 1 1 0 0 1 1 DA0 0 1 0 1 0 1 0 1 Device Position 1st Device on bus 2nd Device on bus 3rd Device on bus 4th Device on bus 5th Device on bus 6th Device on bus 7th Device on bus 8th Device on bus
200 of 269
DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
TDS0SEL Transmit DS0 Channel Monitor Select 189H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 0 5 0 4 TCM4 0 3 TCM3 0 2 TCM2 0 1 TCM1 0 0 TCM0 0
Bit # Name Default
7 0
Bits 7 to 5 : Unused, must be set to zero for proper operation Bits 4 to 0 : Transmit Channel Monitor Bits (TCM[4:0]). TCM0 is the LSB of a 5 bit channel select that determines which transmit channel data will appear in the TDS0M register. Channels 1 through 32 are represented by a 5-bit BCD code from 0 to 31. TCM0 to TCM4 = all 0s selects channel 1, TCM 0 to TCM 4 = 11111 selects channel 32.
Register Name: Register Description: Register Address:
TXPC Transmit Expansion Port Control Register 18AH + (200h x n): where n = 0 to 7, for Ports 1 to 8 6
--
Bit # Name Default
7
--
5
--
4
--
0
0
0
0
3 -0
2 TBPDIR 0
1 TBPFUS 0
0 TBPEN 0
Bit 2 : Transmit BERT Port Direction Control (TBPDIR). 0 = Normal (line) operation. Tx BERT port sources data into the transmit path. 1 = System (Backplane) operation. Tx BERT port sources data into the transmit path (RDATA). In this mode the data on TBPDATA is muxed into the receive path at RDATA (the line side of the e-store). The clock on TBPCLK becomes the clock that was generated for RBPCLK, referenced to RCLK. Bit 1 : Transmit BERT Port Framed/Unframed Select (TBPFUS). 0 = The DS26528's TBP_CLK will not clock data into the F-bit position (framed) 1 = The DS26528's TBP_CLK will clock data into the F-bit position (unframed) Bit 0 : Transmit BERT Port Enable (TBPEN). 0 = Transmit BERT Port is not active 1 = Transmit BERT Port is active.
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
TBPBS Transmit BERT Port Bit Suppress Register 18BH + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 BPBSE7 0 5 BPBSE6 0 4 BPBSE5 0 3 BPBSE4 0 2 BPBSE3 0 1 BPBSE2 0 0 BPBSE1 0
Bit # Name Default
7 BPBSE8 0
Bit 7 : Transmit Channel Bit 8 Suppress (BSE8). MSB of the channel. Set to one to stop this bit from being used. Bit 6 : Transmit Channel Bit 7 Suppress (BSE7). Set to one to stop this bit from being used. Bit 5 : Transmit Channel Bit 6 Suppress (BSE6). Set to one to stop this bit from being used. Bit 4 : Transmit Channel Bit 5 Suppress (BSE5). Set to one to stop this bit from being used Bit 3 : Transmit Channel Bit 4 Suppress (BSE4). Set to one to stop this bit from being used Bit 2 : Transmit Channel Bit 3 Suppress (BSE3). Set to one to stop this bit from being used Bit 1 : Transmit Channel Bit 2 Suppress (BSE2). Set to one to stop this bit from being used Bit 0 : Transmit Channel Bit 1 Suppress (BSE1). LSB of the channel. Set to one to stop this bit from being used.
Register Name: Register Description: Register Address:
TSYNCC Transmit Synchronizer Control Register 18EH + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 0 5 0 4 0 3 CRC4 0 2 TSEN 0 1 SYNCE 0 0 RESYNC 0
Bit # Name Default
7 0
Bit 3 : CRC4 Enable (RCRC4). E1 Mode Only 0 = Do not search for the CRC4 multiframe word 1 = Search for the CRC4 multiframe word Bit 2 : Transmit Synchronizer Enable (TSEN). 0 = Transmit Synchronizer Disabled 1 = Transmit Synchronizer Enabled Bit 1 : Sync Enable (SYNCE). 0 = auto resync enabled 1 = auto resync disabled Bit 0 : Resynchronize (RESYNC). When toggled from low to high, a resynchronization of the transmit side framer is initiated. Must be cleared and set again for a subsequent resync.
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
TLS1 Transmit Latched Status Register 1 190H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 TESEM 5 TSLIP 4 TSLC96 3 TPDV 2 TMF TAF 0 1 LOTCC 0 0 LOTC 0
Bit # Name
7 TESF
Default 0 0 0 0 0 Note: All bits in this register are latched and can cause interrupts.
Bit 7 : Transmit Elastic Store Full Event (TESF). Set when the transmit elastic store buffer fills and a frame is deleted. Bit 6 : Transmit Elastic Store Empty Event (TESEM). Set when the transmit elastic store buffer empties and a frame is repeated. Bit 5 : Transmit Elastic Store Slip Occurrence Event (TSLIP). Set when the transmit elastic store has either repeated or deleted a frame. Bit 4 : Transmit SLC-96 Multiframe Event (TSLC96). T1 Mode Only. When enabled by TCR2.6, this bit will set once per SLC-96 multiframe (72 frames) to alert the host that new data may be written to the TSLC1-TSLC3 registers. See Section 9.9.4.3 for more information. Bit 3 (T1 Mode): Transmit Pulse Density Violation Event (TPDV). Set when the transmit data stream does not meet the ANSI T1.403 requirements for pulse density. Bit 3 (E1 Mode) : Transmit Align Frame Event (TAF). Set every 250ms to alert the host that the TAF and TNAF registers need to be updated. Bit 2 : Transmit Multiframe Event (TMF). In T1 mode, this bit is set every 1.5ms on D4 MF boundaries or every 3ms on ESF MF boundaries. In E1 operation, this but is set every 2ms (regardless if CRC4 is enabled) on transmit multiframe boundaries. Used to alert the host that signaling data needs to be updated. Bit 1 : Loss of Transmit Clock Condition Clear (LOTCC). Set when the LOTC condition has cleared (a clock has been sensed at the TCLK pin). Bit 0 : Loss of Transmit Clock Condition (LOTC). Set when the TCLK pin has not transitioned for approximately 3 clock periods. Will force the LOTC pin high if enabled. This bit can be cleared by the host even if the condition is still present. The LOTC pin will remain high while the condition exists, even if the host has cleared the status bit. If enabled by TIM1.0, the INTB pin will transition low when this bit is set, and transition high when this bit is cleared (if no other unmasked interrupt conditions exist).
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
TLS2 Transmit Latched Status Register 2 (HDLC) 191H + (200h x n): where n = 0 to 7, for Ports 1 to 8 1 TLWMS 0 0 TNFS 0
Bit # 7 6 5 4 3 2 Name TFDLE TUDR TMEND Default 0 0 0 0 0 0 Note: All bits in this register are latched and can create interrupts.
Bit 4 : Transmit FDL Register Empty (TFDLE). T1 Mode Only. Set when the TFDL register has shifted out all 8 bits. Useful if the user wants to manually use the TFDL register to send messages, instead of using the HDLC or BOC controller circuits. Bit 3 : Transmit FIFO Underrun Event (TUDR). Set when the transmit FIFO empties out without having seen the TMEND bit set. An abort is automatically sent. Bit 2 : Transmit Message End Event (TMEND). Set when the transmit HDLC controller has finished sending a message. Bit 1 : Transmit FIFO Below Low Watermark Set Condition (TLWMS). Set when the transmit 64-byte FIFO empties beyond the low watermark as defined by the Transmit Low Watermark Bits (TLWM), (Rising edge detect of TLWM). Bit 0 : Transmit FIFO Not Full Set Condition (TNFS). Set when the transmit 64-byte FIFO has at least one empty byte available for write. Rising edge detect of TNF. Indicates change of state from full to not full.
Register Name: Register Description: Register Address:
TLS3 Transmit Latched Status Register 3 (Synchronizer) 192H + (200h x n): where n = 0 to 7, for Ports 1 to 8 2 0 1 LOF 0 0 LOFD 0
Bit # 7 6 5 4 3 Name Default 0 0 0 0 0 Some bits in this register are latched and can create interrupts.
Bit 1 : Loss of Frame (LOF). A real-time bit that indicates that the transmit synchronizer is searching for the sync pattern in the incoming data stream. Bit 0 : Loss Of Frame Synchronization Detect (LOFD). This latched bit is set when the transmit synchronizer is searching for the sync pattern in the incoming data stream.
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
TIIR Transmit Interrupt Information Register 19FH + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 0 5 0 4 0 3 0 2 TLS3 0 1 TLS2 0 0 TLS1 0
Bit # Name Default
7 0
The interrupt information register provides an indication of which status registers are generating an interrupt. When an interrupt occurs, the host can read TIIR to quickly identify which of the transmit status registers are causing the interrupt(s). These are real-time registers in that the bits will clear once the appropriate interrupt has been serviced and cleared. Bit 2 : Transmit Latched Status Register 3 Interrupt Status (TLS3). 0 = No interrupt pending 1 = Interrupt pending Bit 1 : Transmit Latched Status Register 2 Interrupt Status (TLS2). 0 = No interrupt pending 1 = Interrupt pending Bit 0 : Transmit Latched Status Register 1 Interrupt Status (TLS1). 0 = No interrupt pending 1 = Interrupt pending
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
TIM1 Transmit Interrupt Mask Register 1 1A0H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 TESEM 0 5 TSLIP 0 4 TSLC96 0 3 TPDV TAF 0 2 TMF 0 1 LOTCC 0 0 LOTC 0
Bit # Name Default
7 TESF 0
Bit 7 : Transmit Elastic Store Full Event (TESF). 0 = interrupt masked 1 = interrupt enabled Bit 6 : Transmit Elastic Store Empty Event (TESEM). 0 = interrupt masked 1 = interrupt enabled Bit 5 : Transmit Elastic Store Slip Occurrence Event (TSLIP). 0 = interrupt masked 1 = interrupt enabled Bit 4 : Transmit SLC96 Multiframe Event (TSLC96). T1 Mode Only. 0 = interrupt masked 1 = interrupt enabled Bit 3 (T1 Mode): Transmit Pulse Density Violation Event (TPDV). 0 = interrupt masked 1 = interrupt enabled Bit 3 (E1 Mode): Transmit Align Frame Event (TAF). 0 = interrupt masked 1 = interrupt enabled Bit 2 : Transmit Multiframe Event (TMF). 0 = interrupt masked 1 = interrupt enabled Bit 1 : Loss of Transmit Clock Clear Condition (LOTCC). 0 = interrupt masked 1 = interrupt enabled Bit 0 : Loss of Transmit Clock Condition (LOTC). 0 = interrupt masked 1 = interrupt enabled
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
TIM2 Transmit Interrupt Mask Register 2 1A1H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 0 5 0 4 TFDLE 0 3 TUDR 0 2 TMEND 0 1 TLWMS 0 0 TNFS 0
Bit # Name Default
7 0
Bit 4 : Transmit FDL Register Empty (TFDLE). T1 Mode Only. 0 = interrupt masked 1 = interrupt enabled Bit 3 : Transmit FIFO Underrun Event (TUDR). 0 = interrupt masked 1 = interrupt enabled Bit 2 : Transmit Message End Event (TMEND). 0 = interrupt masked 1 = interrupt enabled Bit 1 : Transmit FIFO Below Low WaterMark Set Condition (TLWMS). 0 = interrupt masked 1 = interrupt enabled Bit 0 : Transmit FIFO Not Full Set Condition (TNFS). 0 = interrupt masked 1 = interrupt enabled
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
TIM3 Transmit Interrupt Mask Register 3 (Synchronizer) 1A2H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 0 5 0 4 0 3 0 2 0 1 0 0 LOFD 0
Bit # Name Default
7 0
Bit 0 : Loss Of Frame Synchronization Detect (LOFD). 0 = Interrupt Masked 1 = Interrupt Enabled
Register Name: Register Description: Register Address:
T1TCD1 Transmit Code Definition Register 1 1ACH + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0
Bit # Name Default
7 C7 0
Bit 7 : Transmit Code Definition Bit 7 (C7). First bit of the repeating pattern. Bit 6 : Transmit Code Definition Bit 6 (C6). Bit 5 : Transmit Code Definition Bit 5 (C5). Bit 4 : Transmit Code Definition Bit 4 (C4). Bit 3 : Transmit Code Definition Bit 3 (C3). Bit 2 : Transmit Code Definition Bit 2 (C2). A Don't Care if a 5 bit length is selected. Bit 1 : Transmit Code Definition Bit 1 (C1). A Don't Care if a 5 or 6 bit length is selected. Bit 0 : Transmit Code Definition Bit 0 (C0). A Don't Care if a 5, 6 or 7 bit length is selected.
Register Name: Register Description: Register Address:
T1TCD2 Transmit Code Definition Register 2 1ADH + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0
Bit # Name Default
7 C7 0
Bit 7 : Transmit Code Definition Bit 7 (C7). A Don't Care if a 5, 6 or 7 bit length is selected. Bit 6 : Transmit Code Definition Bit 6 (C6). A Don't Care if a 5, 6 or 7 bit length is selected. Bit 5 : Transmit Code Definition Bit 5 (C5). A Don't Care if a 5, 6 or 7 bit length is selected. Bit 4 : Transmit Code Definition Bit 4 (C4). A Don't Care if a 5, 6 or 7 bit length is selected. Bit 3 : Transmit Code Definition Bit 3 (C3). A Don't Care if a 5, 6 or 7 bit length is selected. Bit 2 : Transmit Code Definition Bit 2 (C2). A Don't Care if a 5, 6 or 7 bit length is selected. Bit 1 : Transmit Code Definition Bit 1 (C1). A Don't Care if a 5, 6 or 7 bit length is selected. Bit 0 : Transmit Code Definition Bit 0 (C0). A Don't Care if a 5, 6 or 7 bit length is selected.
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Register Name: Register Description: Register Address:
TRTS2 Transmit Real-Time Status Register 2 (HDLC) 1B1H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 0 5 0 4 0 3 TEMPTY 0 2 TFULL 0 1 TLWM 0 0 TNF 0
Bit # Name Default
7 0
Note:All bits in this register are real time. Bit 3 : Transmit FIFO Empty (TEMPTY). A real-time bit that is set high when the FIFO is empty. Bit 2 : Transmit FIFO Full (TFULL). A real-time bit that is set high when the FIFO is full. Bit 1 : Transmit FIFO Below Low Watermark Condition (TLWM). Set when the transmit 64-byte FIFO empties beyond the low watermark as defined by the Transmit Low Watermark Bits (TLWM). Bit 0 : Transmit FIFO Not Full Condition (TNF). Set when the transmit 64-byte FIFO has at least one byte available.
Register Name: Register Description: Register Address:
TFBA Transmit HDLC FIFO Buffer Available 1B3H + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 TFBA6 0 5 TFBA5 0 4 TFBA4 0 3 TFBA3 0 2 TFBA2 0 1 TFBA1 0 0 TFBA0 0
Bit # Name Default
7 -0
Bits 6 to 0 : Transmit FIFO Bytes Available (TFBA6 to TFBA0). TFBA0 is the LSB.
Register Name:
Register Description:
Register Address:
THF Transmit HDLC FIFO 1B4 + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 THD6 0 5 THD5 0 4 THD4 0 3 THD3 0 2 THD2 0 1 THD1 0 0 THD0 0
Bit # Name Default
7 THD7 0
Bit 7 : Transmit HDLC Data Bit 7 (THD7). MSB of a HDLC packet data byte. Bit 6 : Transmit HDLC Data Bit 6 (THD6). Bit 5 : Transmit HDLC Data Bit 5 (THD5). Bit 4 : Transmit HDLC Data Bit 4 (THD4). Bit 3 : Transmit HDLC Data Bit 3 (THD3). Bit 2 : Transmit HDLC Data Bit 2 (THD2). Bit 1 : Transmit HDLC Data Bit 1 (THD1). Bit 0 : Transmit HDLC Data Bit 0 (THD0). LSB of a HDLC packet data byte.
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Register Name: Register Description: Register Address:
TDS0M Transmit DS0 Monitor Register 1BBH + (200h x n): where n = 0 to 7, for Ports 1 to 8 6 B2 0 5 B3 0 4 B4 0 3 B5 0 2 B6 0 1 B7 0 0 B8 0
Bit # Name Default
7 B1 0
Bits 7 to 0 : Transmit DS0 Channel Bits (B1 to B8). Transmit channel data that has been selected by the Transmit Channel Monitor Select Register. B8 is the LSB of the DS0 channel (last bit to be transmitted).
Register Name: Register Description: Register Address:
TBCS1, TBCS2, TBCS3, TBCS4 Transmit Blank Channel Select Registers 1C0H, 1C1H, 1C2H, 1C3H + (200h x n): where n = 0 to 7, for Ports 1 to 8 (LSB) CH1 CH9 CH17 CH25
(MSB) CH8 CH16 CH24 CH32
CH7 CH15 CH23 CH31
CH6 CH14 CH22 CH30
CH5 CH13 CH21 CH29
CH4 CH12 CH20 CH28
CH3 CH11 CH19 CH27
CH2 CH10 CH18 CH26
TBCS1 TBCS2 TBCS3 TBCS4
Bits 7 to 0 : Transmit Blank Channel Select for Channels 1 to 32 (TBCS1 to TBCS32). 0 = transmit TSER data from this channel 1 = ignore TSER data from this channel Note that when two or more sequential channels are chosen to be ignored, the receive slip zone select bit should be set to zero. If the ignore channels are distributed (such as 1, 5, 9, 13, 17, 21, 25, 29) then the RSZS bit can be set to one, which may provide a lower occurrence of slips in certain applications.
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Register Name: Register Description: Register Address:
TCBR1, TCBR2, TCBR3, TCBR4 Transmit Channel Blocking Registers 1C4H, 1C5H, 1C6H, 1C7H + (200h x n): where n = 0 to 7, for Ports 1 to 8 (LSB) CH1 CH9 CH17 CH25: Fbit
(MSB) CH8 CH16 CH24 CH32
CH7 CH15 CH23 CH31
CH6 CH14 CH22 CH30
CH5 CH13 CH21 CH29
CH4 CH12 CH20 CH28
CH3 CH11 CH19 CH27
CH2 CH10 CH18 CH26
TCBR1 TCBR2 TCBR3 TCBR4*
Bits 7 to 0 : Transmit Channels 1 to 32 Channel Blocking Control Bits (CH1 to CH32). 0 = force the TCHBLK pin to remain low during this channel time 1 = force the TCHBLK pin high during this channel time * Note that TCBR4 has two functions: When 2.048MHz backplane mode is selected, this register allows the user to enable the channel blocking signal for any of the 32 possible backplane channels. When 1.544MHz backplane mode is selected, the LSB of this register determines whether or not the TCHBLK signal will pulse high during the F-Bit time: TCBR4.0 = 0, do not pulse TCHBLK during the F-Bit TCBR4.0 = 1, pulse TCHBLK during the F-Bit In this mode TCBR4.1 to TCBR4.7 should be set to '0'.
Register Name: Register Description: Register Address: (MSB) CH8 CH16 CH24 CH32
THSCS1, THSCS2, THSCS3, THSCS4 Transmit Hardware Signaling Channel Select Registers 1C8H, 1C9H, 1CAH, 1CBH + (200h x n): where n = 0 to 7, for Ports 1 to 8 (LSB) CH1 CH9 CH17 CH25
CH7 CH15 CH23 CH31
CH6 CH14 CH22 CH30
CH5 CH13 CH21 CH29
CH4 CH12 CH20 CH28
CH3 CH11 CH19 CH27
CH2 CH10 CH18 CH26
THSCS1 THSCS2 THSCS3 THSCS4*
Bits 7 to 0 : Transmit Hardware Signaling Channel Select for Channels 1 to 32 (THSCS1 to THSCS4). These bits determine which channels have signaling data inserted from the TSIG pin into the TSER PCM data. 0 = do not source signaling data from the TSIG pin for this channel 1 = source signaling data from the TSIG pin for this channel * Note that THSCS4 is only used in 2.048MHz backplane applications.
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Register Name: Register Description: Register Address:
TGCCS1, TGCCS2, TGCCS3, TGCCS4 Transmit Gapped Clock Channel Select Registers 1CCH, 1CDH, 1CEH, 1CFH + (200h x n): where n = 0 to 7, for Ports 1 to 8 (LSB) CH1 CH9 CH17 CH25: Fbit
(MSB) CH8 CH16 CH24 CH32
CH7 CH15 CH23 CH31
CH6 CH14 CH22 CH30
CH5 CH13 CH21 CH29
CH4 CH12 CH20 CH28
CH3 CH11 CH19 CH27
CH2 CH10 CH18 CH26
TGCCS1 TGCCS2 TGCCS3 TGCCS4*
Bits 7 to 0 : Transmit Channels 1 to 32 Gapped Clock Channel Select Bits (CH1 to CH32). 0 = no clock is present on TCHCLK during this channel time 1 = force a clock on TCHCLK during this channel time. The clock will be synchronous with TCLK if the elastic store is disabled, and synchronous with TSYSCLK if the elastic store is enabled. * Note that TGCCS4 has two functions: When 2.048MHz backplane mode is selected, this register allows the user to enable the 'gapped' clock on TCHCLK for any of the 32 possible backplane channels. When 1.544MHz backplane mode is selected, the LSB of this register determines whether or not a clock is generated on TCHCLK during the F-Bit time: TGCCS4.0 = 0, do not generate a clock during the F-Bit TGCCS4.0 = 1, generate a clock during the F-Bit In this mode TGCCS4.1 to TGCCS4.7 should be set to '0'.
Register Name: Register Description: Register Address:
PCL1, PCL2, PCL3, PCL4 Per-Channel Loopback Enable Registers 1D0H, 1D1H, 1D2H, 1DH3 + (200h x n): where n = 0 to 7, for Ports 1 to 8 (LSB) CH1 CH9 CH17 CH25
(MSB) CH8 CH16 CH24 CH32
CH7 CH15 CH23 CH31
CH6 CH14 CH22 CH30
CH5 CH13 CH21 CH29
CH4 CH12 CH20 CH28
CH3 CH11 CH19 CH27
CH2 CH10 CH18 CH26
PCL1 PCL2 PCL3 PCL4
Bits 7 to 0 : Per-Channel Loopback Enable for Channels 32 to 1 (CH32 to CH1). 0 = Loopback disabled 1 = Enable Loopback. Source data from the corresponding receive channel
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Register Name: Register Description: Register Address:
TBPCS1, TBPCS2, TBPCS3, TBPCS4 Transmit BERT Port Channel Select Registers 1D4H, 1D5H, 1D6H, 1D7H + (200h x n): where n = 0 to 7, for Ports 1 to 8 (LSB) CH1 CH9 CH17 CH25
(MSB) CH8 CH16 CH24 CH32
CH7 CH15 CH23 CH31
CH6 CH14 CH22 CH30
CH5 CH13 CH21 CH29
CH4 CH12 CH20 CH28
CH3 CH11 CH19 CH27
CH2 CH10 CH18 CH26
TBPCS1 TBPCS2 TBPCS3 TBPCS4
Setting any of the CH1 through CH24 bits in the TBPCS1 through TBPCS3 registers will enable the TBP_CLK for the associated channel time, and allow mapping of the selected channel data out of the receive BERT Port. Multiple, or all channels may be selected simultaneously.
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10.5 LIU Register Definitions Table 10-13. LIU Register Set
ADDR ABBR DESCRIPTION 1000 LTRCR LIU Transmit Receive Control Register 1001 LTITSR LIU Transmit Impedance Selection Register 1002 LMCR LIU Maintenance Control Register 1003 LRSR LIU Real Status Register 1004 LSIMR LIU Status Interrupt Mask Register 1005 LLSR LIU Latched Status Register 1006 LRSL LIU Receive Signal Level 1007 LRISMR LIU Receive Impedance and Sensitivity Monitor Register 1008-101F Reserved Note: Reserved registers should only be written with all zeros.
Register Name: Register Description: Register Addresses:
R/W R/W R/W R/W R R/W R/W R R/W -
LTRCR LIU Transmit Receive Control Register 1000H + (20h x n): where n = 0 to 7, for Ports 1 to 8 6 -0 5 -0 4 JADS 0 3 JAPS1 0 2 JAPS0 0 1 T1J1E1S 0 0 LSC 0
Bit # Name Default
7 -0
Bit 4 : Jitter Attenuator Depth Select (JADS). 0 = JA FIFO depth set to 128 bits. 1 = JA FIFO depth set to 32 bits. Use for delay-sensitive applications. Bit 3, 2 : Jitter Attenuator Position Select 1, 0 (JAPS[1:0]). These bits are used to select the position of the jitter attenuator (JA). JAPS1 0 0 1 1 JAPS0 0 1 0 1 Function JA in the receive path JA in the transmit path JA is not used JA is not used
Bit 1 : T1J1E1 Selection (T1J1E1S). This bit configures the LIU for E1 or T1/J1 operation. 0 = E1 1 = T1 or J1 Bit 0 : LOS Criteria Selection (LCS). This bit is used for LIU LOS Selection Criteria. E1 Mode 0 = G.775. 1 = ETSI (300233). T1 / J1 Mode 0 = T1.231. 1 = T1.231.
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Register Name: Register Description: Register Address:
LTITSR LIU Transmit Impedance and Pulse Shape Selection Register 1001H + (20h x n): where n = 0 to 7, for Ports 1 to 8 6 TIMPTOFF 0 5 TIMPL1 0 4 TIMPL0 0 3 -0 2 L2 0 1 L1 0 0 L0 0
Bit # Name Default
7 -0
Bit 6 : Transmit Impedance Off (TIMPTOFF). 0 = Enable transmit terminating impedance. 1 = Disable transmit terminating impedance. Bits 5, 4 : Transmit Load Impedance 1, 0 (TIMPL[1:0]). These bits are used to select the transmit load impedance. These must be set to match the cable impedance. Even if the Internal load impedance is turned off (via TIMPTOFF); the external cable impedance has to be specified for optimum operation. For J1 applications, use 110W. See Table 10-14. Bits 2 to 0 : Line Build-Out Select 2 to 0 (L[2:0]). Used to select the transmit waveshape. The waveshape has a voltage level and load impedance associated with it once the T1/J1 or E1 selection is made by settings in the LTRCR register. See Table 10-15.
Table 10-14. Transmit Load Impedance Selection
TIMPL1 0 0 1 1 TIMPLO 0 1 0 1 IMPEDANCE SELECTION 75W 100W 110W 120W
Table 10-15. Transmit Pulse Shape Selection
L2 0 0 L1 0 0 L0 0 1 MODE E1 E1 IMPEDANCE 75W 120W NOMINAL VOLTAGE 2.37V 3.0V
L2 0 0 0 0 1 1 1 1
L1 0 0 1 1 0 0 1 1
L0 0 1 0 1 0 1 0 1
MODE T1/J1 T1/J1 T1/J1 T1/J1 T1/J1 T1/J1 T1/J1 T1/J1
CABLE LENGTH DSX-1/0dB CSU, 0ft-133ft ABAM 100W DSX-1, 133ft-266ft ABAM 100W DSX-1, 266ft-399ft ABAM 100W DSX-1, 399ft-533ft ABAM 100W DSX-1, 533ft-655ft ABAM 100W -7.5dB CSU -15dB CSU -22.5dB CSU
MAX ALLOWED CABLE LOSS 0.6dB 1.2dB 1.8dB 2.4dB 3.0dB
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Register Name: Register Description: Register Address:
LMCR LIU Maintenance Control Register 1002H + (20h x n): where n = 0 to 7, for Ports 1 to 8 6 ATAIS 0 5 LLB 0 4 ALB 0 3 RLB 0 2 TPDE 0 1 RPDE 0 0 TE 0
Bit # Name Default
7 TAIS 0
Bit 7 : Transmit AIS (TAIS). Alarm Indication Signal (AIS) is sent using MCLK as the reference clock. The transmit data coming from the framer is ignored. 0 = TAIS is disabled. 1 = Output an unframed all ones pattern (AIS) at TTIP and TRING. Bit 6 : Automatic Transmit AIS (ATAIS). 0 = ATAIS is disabled. 1 = Automatically transmit AIS on the occurrence of a LIU LOS. Bit 5 : Local Loopback (LLB). See Section 9.11.5.2 Local Loopback for operational details. 0 = LLB is disabled. 1 = LLB is enabled. Bit 4 : Analog Loopback (ALB). See Section 9.11.5.1 Analog Loopback for operational details. 0 = ALB is disabled. 1 = ALB is enabled. Bit 3 : Remote Loopback (RLB). See Section 9.11.5.3 Remote Loopback for operational details. 0 = Remote loopback is disabled. 1 = Remote loopback is enabled. In this loopback, received data passes all the way through the receive LIU and is then transmitted back trough the transmit side of the LIU. Data will continue to pass through the receive side framer of the DS26528 as it would normally and the data from the transmit side of the framer will be ignored. Bit 2 : Transmit Power-Down Enable (TPDE). 0 = Transmitter power enabled. 1 = Transmitter powered down. TIP/RING outputs are High-Z. Bit 1 : Receiver Power-Down Enable (RPDE). 0 = Receiver power enabled. 1 = Receiver powered down. Bit 0 : Transmit Enable (TE). This function is overridden by the TXENABLE pin. 0 = TTIP/TRING outputs are High-Z. 1 = TTIP/TRING outputs enabled.
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Register Name: Register Description: Register Address:
LRSR LIU Real Status Register 1003H + (20h x n): where n = 0 to 7, for Ports 1 to 8 6 -0 5 OEQ 0 4 UEQ 0 3 -0 2 SCS 0 1 OCS 0 0 LOSS 0
Bit # Name Default
7 -0
Bit 5 : Over Equalized (OEQ). The equalizer is over equalized. This can happen if there very large unexpected resistive loss. This could result if monitor mode is used and the device is not placed in monitor mode. This indicator provides more qualitative information to the receive loss indicators. Bit 4 : Under Equalized (UEQ). The equalizer is under equalized. A signal with a very high resistive gain is being applied. This indicator provides more qualitative information to the receive loss indicators. Bit 2: Short Circuit Status (SCS). A real-time bit set when the LIU detects that the TTIP and TRING outputs are short-circuited. The load resistance has to be 25W (typically) or less for short circuit detection. Bit 1: Open Circuit Status (OCS). A real-time bit set when the LIU detects that the TTIP and TRING outputs are open-circuited. Bit 0: Loss of Signal Status (LOS). A real-time bit set when the LIU detects a LOS condition at RTIP and RRING.
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Register Name: Register Description: Register Address:
LSIMR LIU Status Interrupt Mask Register 1004H + (20h x n): where n = 0 to 7, for Ports 1 to 8 6 OCCIM 0 5 SCCIM 0 4 LOSCIM 0 3 JALTSIM 0 2 OCDIM 0 1 SCDIM 0 0 LOSDIM 0
Bit # Name Default
7 JALTCIM 0
Bit 7 : Jitter Attenuator Limit Trip Clear Interrupt Mask (JALTCIM).
0 = Interrupt masked. 1 = Interrupt enabled. Bit 6 : Open Circuit Clear Interrupt Mask (OCCIM). 0 = Interrupt masked. 1 = Interrupt enabled. Bit 5 : Short Circuit Clear Interrupt Mask (SCCIM). 0 = Interrupt masked. 1 = Interrupt enabled. Bit 4 : Loss of Signal Clear Interrupt Mask (LOSCIM). 0 = Interrupt masked. 1 = Interrupt enabled. Bit 3 : Jitter Attenuator Limit Trip Set Interrupt Mask (JALTSIM). 0 = Interrupt masked. 1 = Interrupt enabled. Bit 2 : Open Circuit Detect Interrupt Mask (OCDIM). 0 = Interrupt masked. 1 = Interrupt enabled. Bit 1 : Short Circuit Detect Interrupt Mask (SCDIM). 0 = Interrupt masked. 1 = Interrupt enabled. Bit 0 : Loss of Signal Detect Interrupt Mask (LOSDIM). 0 = Interrupt masked. 1 = Interrupt enabled.
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Register Name: Register Description: Register Address:
LLSR LIU Latched Status Register 1005H + (20h x n): where n = 0 to 7, for Ports 1 to 8 2 OCD 0 1 SCD 0 0 LOSD 0
Bit # 7 6 5 4 3 Name JALTC OCC SCC LOSC JALTS Default 0 0 0 0 0 All bits in this register are latched and can create interrupts.
Bit 7 : Jitter Attenuator Limit Trip Clear (JALTC). This latched bit is set when a JA limit trip condition was detected and then removed. Bit 6 : Open Circuit Clear (OCC). This latched bit is set when an open circuit condition was detected at TTIP and TRING and then removed. Bit 5: Short Circuit Clear (SCC). This latched bit is set when a short circuit condition was detected at TTIP and TRING and then removed. Bit 4 : Loss of Signal Clear (LOSC). This latched bit is set when a loss of signal condition was detected at RTIP and RRING and then removed. Bit 3 : Jitter Attenuator Limit Trip Set (JALTS). This latched bit is set when the jitter attenuator trip condition is detected. Bit 2 : Open Circuit Detect (OCD). This latched bit when set when open circuit condition is detected at TTIP and TRING. This bit is not functional in T1 CSU operating modes (T1 LBO 5, LBO 6, and LBO 7). Bit 1 : Short Circuit Detect (SCD). This latched bit is set when short circuit condition is detected at TTIP and TRING. This bit is not functional in T1 CSU operating modes (T1 LBO 5, LBO 6, and LBO 7). Bit 0 : Loss of Signal Detect (LOSD). This latched bit is set when LOS condition is detected at RTIP and RRING.
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Register Name: Register Description: Register Address:
LRSL LIU Receive Signal Level 1006H + (20h x n): where n = 0 to 7, for Ports 1 to 8 6 RSL2 0 5 RLS1 0 4 RLS0 0 3 -0 2 -0 1 -0 0 -0
Bit # Name Default
7 RSL3 0
Bit 7 to 4 : Receiver Signal Level 3 to 0 (RSL[3:0]). Real-time receive signal level as shown in Table 10-16. Note
that the range of signal levels reported the RSL0-3 is limited by the Equalizer Gain Limit (EGL) in short-haul applications.
Table 10-16. Receive Level Indication
RSL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RSL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RSL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RSL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 RECEIVE LEVEL (dB) T1 >-2.5 -2.5 to -5 -5 to -7.5 -7.5 to -10 -10 to -12.5 -12.5 to -15 -15 to -17.5 -17.5 to -20 -20 to -23 -23 to -26 -26 to -29 -29 to -32 -32 to -36 <-36 E1 >-2.5 -2.5 to -5 -5 to -7.5 -7.5 to -10 -10 to -12.5 -12.5 to -15 -15 to -17.5 -17.5 to -20 -20 to -23 -23 to -26 -26 to -29 -29 to -32 -32 to -36 -36 to -40 -40 to -44 <-44
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Register Name: Register Description: Register Address:
LRISMR LIU Receive Impedance and Sensitivity Monitor Register 1007H + (20h x n): where n = 0 to 7, for Ports 1 to 8 6 RIMPOFF 0 5 RIMPM1 0 4 RIMPM0 0 3 RTR 0 2 RMONEN 0 1 RSMS1 0 0 RSMS0 0
Bit # Name Default
7 RG703 0
Bit 7 : Receive G.703 Clock (RG703). If this bit is set, the receiver expects a 2.048MHz or 1.544MHz clock from the RTIP/RRING, based on the selection of T1 (1.544) or E1 (2.048) mode in the LTRCR register. Bit 6 : Receive Impedance Termination Off (RIMPOFF). 0 = Receive terminating impedance match is enabled. 1 = Receive terminating impedance match is disabled. Bit 5, 4 : Receive Impedance Match 1, 0 (RIMPM[1:0]).These bits are used to select the receive impedance match value. These must be set according to the Cable Impedance. Even if the Internal Receive Match Impedance is turned off (RIMOFF); the external cable impedance has to be specified for optimum operation by RIMPM1 to 0. See Table 10-17. Bit 3 : Receiver Turns Ratio (RTR). 0 = Receive transformer turns ratio is 1:1. 1 = Receive transformer turns ratio is 2:1. This option should only be used in short haul applications. Bit 2 : Receiver Monitor Mode Enable (RMONEN). 0 = Disable receive monitor mode. 1 = Enable receive monitor mode. Resistive gain is added with the maximum sensitivity. The receiver sensitivity is determined by RSMS1 and RSMS0 Bit 1, 0 : Receiver Sensitivity / Monitor Gain Select 1, 0 (RSMS[1:0]). These bits are used to select the receiver sensitivity level and additional gain in monitoring applications. The monitor mode (RMONEN) adds resistive gain to compensate for the signal loss caused by the isolation resistors. See Table 10-18 and Table 10-19.
Table 10-17. Receive Impedance Selection
RIMPRM1, RIMPRM0 00 01 10 11 RECEIVE IMPEDANCE SELECTED (W) 75 100 110 120
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Table 10-18. Receiver Sensitivity Selection with Monitor Mode Disabled
RMONEN 0 0 0 0 RSMS [1:0] 00 01 10 11 RECEIVER MONITOR MODE GAIN (dB) 0 0 0 0 RECEIVER SENSITIVITY (MAX CABLE LOSS ALLOWED) (dB) 12 18 30 36 for T1; 43 for E1
Table 10-19. Receiver Sensitivity Selection with Monitor Mode Enabled
RMONEN 1 1 1 1 RSMS [1:0] 00 01 10 11 RECEIVER MONITOR MODE GAIN (dB) 14 20 26 32 RECEIVER SENSITIVITY (MAX CABLE LOSS ALLOWED) (dB) 30 22.5 17.5 12
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10.6 BERT Register Definitions Table 10-20. BERT Register Set
ADDR 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 110A 110B 110C 110D 110E 110F ABBR BAWC BRP1 BRP2 BRP3 BRP4 BC1 BC2 BBC1 BBC2 BBC3 BBC4 BEC1 BEC2 BEC3 BLSR BSIM DESCRIPTION BERT Alternating Word Count Rate BERT Repetitive Pattern Set Register 1 BERT Repetitive Pattern Set Register 2 BERT Repetitive Pattern Set Register 3 BERT Repetitive Pattern Set Register 4 BERT Control Register 1 BERT Control Register 2 BERT Bit Count Register 1 BERT Bit Count Register 2 BERT Bit Count Register 3 BERT Bit Count Register 4 BERT Error Count Register 1 BERT Error Count Register 2 BERT Error Count Register 3 BERT Status Register BERT Status Interrupt Mask R/W R R/W R/W R/W R/W R/W R/W R R R R R R R R R/W
Register Name: Register Description: Register Address:
BAWC BERT Alternating Word Count Rate 1100H + (10h x n): where n = 0 to 7, for Ports 1 to 8 6 ACNT6 0 5 ACNT5 0 4 ACNT4 0 3 ACNT3 0 2 ACNT2 0 1 ACNT1 0 0 ACNT0 0
Bit # Name Default
7 ACNT7 0
Bits 7 to 0: Alternating Word Count Rate Bits 7 to 0 (ACNT[7:0]). When the BERT is programmed in the alternating word mode, the words will repeat for the count loaded into this register then flip to the other word and again repeat for the number of times loaded into this register. ACNT0 is the LSB of the 8-bit alternating word count rate counter.
Register Name: Register Description: Register Address:
BRP1 BERT Repetitive Pattern Set Register 1 1101H + (10h x n): where n = 0 to 7, for Ports 1 to 8 6 RPAT6 0 5 RPAT5 0 4 RPAT4 0 3 RPAT3 0 2 RPAT2 0 1 RPAT1 0 0 RPAT0 0
Bit # Name Default
7 RPAT7 0
Bits 7 to 0: BERT Repetitive Pattern Set Bits 7 to 0 (RPAT[7:0]). RPAT0 is the LSB of the 32-bit repetitive pattern.
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Register Name: Register Description: Register Address:
BRP2 BERT Repetitive Pattern Set Register 2 1102H + (10h x n): where n = 0 to 7, for Ports 1 to 8 6 RPAT14 0 5 RPAT13 0 4 RPAT12 0 3 RPAT11 0 2 RPAT10 0 1 RPAT9 0 0 RPAT8 0
Bit # Name Default
7 RPAT15 0
Bits 7 to 0: BERT Repetitive Pattern Set Bits 15 to 8 (RPAT[15:8]).
Register Name: Register Description: Register Address:
BRP3 BERT Repetitive Pattern Set Register 3 1103H + (10h x n): where n = 0 to 7, for Ports 1 to 8 6 RPAT22 0 5 RPAT21 0 4 RPAT20 0 3 RPAT19 0 2 RPAT18 0 1 RPAT17 0 0 RPAT16 0
Bit # Name Default
7 RPAT23 0
Bits 7 to 0 : BERT Repetitive Pattern Set Bits 23 to 16 (RPAT[23:16]).
Register Name: Register Description: Register Address:
BRP4 BERT Repetitive Pattern Set Register 4 1104H + (10h x n): where n = 0 to 7, for Ports 1 to 8 6 RPAT30 0 5 RPAT29 0 4 RPAT28 0 3 RPAT27 0 2 RPAT26 0 1 RPAT25 0 0 RPAT24 0
Bit # Name Default
7 RPAT31 0
Bits 7 to 0 : BERT Repetitive Pattern Set Bits 31 to 24 (RPAT[31:24]). RPAT31 is the MSB of the 32-bit repetitive pattern.
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DS26528 Octal T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 TC 0 BC1 BERT Control Register 1 1105H + (10h x n): where n = 0 to 7, for Ports 1 to 8 6 TINV 0 5 RINV 0 4 PS2 0 3 PS1 0 2 PS0 0 1 LC 0 0 RESYNC 0
Bit 7: Transmit Pattern Load (TC). A low-to-high transition loads the pattern generator with the pattern that is to be generated. This bit should be toggled from low to high whenever the host wishes to load a new pattern. Must be cleared and set again for a subsequent loads. Bit 6:Transmit Invert Data Enable (TINV). 0 = do not invert the outgoing data stream 1 = invert the outgoing data stream Bit 5:Receive Invert Data Enable (RINV). 0 = do not invert the incoming data stream 1 = invert the incoming data stream Bits 4 to 2: Pattern Select Bits 2 to 0 (PS[2:0]). These bits select data pattern used by the transmit and receive circuits. See Table 10-21.
Table 10-21. BERT Pattern Select
PS2 0 0 0 0 1 1 1 1 PS1 0 0 1 1 0 0 1 1 PS0 0 1 0 1 0 1 0 1 PATTERN DEFINITION Pseudo-Random 2E7-1 Pseudo-Random 2E11-1 Pseudo-Random 2E15-1 20 Pseudo-Random Pattern QRSS. A 2 - 1 pattern with 14 consecutive zero restriction. Repetitive Pattern Alternating Word Pattern Modified 55 Octet (Daly) Pattern. The Daly pattern is a repeating 55 octet pattern that is byte-aligned into the active DS0 time slots. The pattern is defined in an ATIS (Alliance for Telecommunications Industry Solutions) Committee T1 Technical Report Number 25 (November 1993). Pseudo-Random 2E-9-1
Bit 1: Load Bit and Error Counters (LC). A low-to-high transition latches the current bit and error counts into the registers BBC1, BBC2, BBC3, BBC4 and BEC1, BEC2, BEC3 and clears the internal count. This bit should be toggled from low to high whenever the host wishes to begin a new acquisition period. Must be cleared and set again for a subsequent loads. Bit 0: Force Resynchronization (RESYNC). A low-to-high transition will force the receive BERT synchronizer to resynchronize to the incoming data stream. This bit should be toggled from low to high whenever the host wishes to acquire synchronization on a new pattern. Must be cleared and set again for a subsequent resynchronization.
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
BC2 BERT Control Register 2 1106H + (10h x n): where n = 0 to 7, for Ports 1 to 8 6 EIB1 0 5 EIB0 0 4 SBE 0 3 RPL3 0 2 RPL2 0 1 RPL1 0 0 RPL0 0
Bit # Name Default
7 EIB2 0
Bits 7 to 5: Error Insert Bits 2 to 0 (EIB[2:0]). Will automatically insert bit errors at the prescribed rate into the generated data pattern. Can be used for verifying error detection features. See Table 10-22.
Table 10-22. BERT Error Insertion Rate
EIB2 0 0 0 0 1 1 1 1 EIB1 0 0 1 1 0 0 1 1 EIB0 0 1 0 1 0 1 0 1 ERROR RATE INSERTED No errors automatically inserted 10E-1 10E-2 10E-3 10E-4 10E-5 10E-6 10E-7
Bit 4: Single Bit Error Insert (SBE). A low-to-high transition will create a single bit error. Must be cleared and set again for a subsequent bit error to be inserted. Bits 3 to 0: Repetitive Pattern Length Select 3 to 0 (RPL[3:0]). RPL0 is the LSB and RPL3 is the MSB of a nibble that describes the how long the repetitive pattern is. The valid range is 17 (0000) to 32 (1111). These bits are ignored if the receive BERT is programmed for a pseudo-random pattern. To create repetitive patterns less than 17 bits in length, the user must set the length to an integer number of the desired length that is less than or equal to 32. For example, to create a 6-bit pattern, the user can set the length to 18 (0001) or to 24 (0111) or to 30 (1101). See Table 10-23.
Table 10-23. BERT Repetitive Pattern Length Select
LENGTH (BITS) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RPL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RPL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 RPL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 RPL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
BBC1 BERT Bit Count Register 1 1107H + (10h x n): where n = 0 to 7, for Ports 1 to 8 6 BBC6 0 5 BBC5 0 4 BBC4 0 3 BBC3 0 2 BBC2 0 1 BBC1 0 0 BBC0 0
Bit # Name Default
7 BBC7 0
Bits 7 to 0: BERT Bit Counter Bits 7 to 0 (BBC[7:0]). BBC0 is the LSB of the 32-bit counter.
Register Name: Register Description: Register Address:
BBC2 BERT Bit Count Register 2 1108H + (10h x n): where n = 0 to 7, for Ports 1 to 8 6 BBC14 0 5 BBC13 0 4 BBC12 0 3 BBC11 0 2 BBC10 0 1 BBC9 0 0 BBC8 0
Bit # Name Default
7 BBC15 0
Bits 7 to 0: BERT Bit Counter Bits 15 to 8 (BBC[15:8]).
Register Name: Register Description: Register Address:
BBC3 BERT Bit Count Register 3 1109H + (10h x n): where n = 0 to 7, for Ports 1 to 8 6 BBC22 0 5 BBC21 0 4 BBC20 0 3 BBC19 0 2 BBC18 0 1 BBC17 0 0 BBC16 0
Bit # Name Default
7 BBC23 0
Bits 7 to 0: BERT Bit Counter Bits 23 to 16 (BBC[23:16]).
Register Name: Register Description: Register Address:
BBC4 BERT Bit Count Register 4 110AH + (10h x n): where n = 0 to 7, for Ports 1 to 8 6 BBC30 0 5 BBC29 0 4 BBC28 0 3 BBC27 0 2 BBC26 0 1 BBC25 0 0 BBC24 0
Bit # Name Default
7 BBC31 0
Bits 7 to 0: BERT Bit Counter Bits 31 to 24 (BBC[31:24]). BBC31 is the MSB of the 32-bit counter.
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
BEC1 BERT Error Count Register 1 110BH + (10h x n): where n = 0 to 7, for Ports 1 to 8 6 EC6 0 5 EC5 0 4 EC4 0 3 EC3 0 2 EC2 0 1 EC1 0 0 EC0 0
Bit # Name Default
7 EC7 0
Bits 7 to 0: Error Counter Bits 7 to 0 (EC[7:0]). EC0 is the LSB of the 24-bit counter.
Register Name: Register Description: Register Address:
BEC2 BERT Error Count Register 2 110CH + (10h x n): where n = 0 to 7, for Ports 1 to 8 6 EC14 0 5 EC13 0 4 EC12 0 3 EC11 0 2 EC10 0 1 EC9 0 0 EC8 0
Bit # Name Default
7 EC15 0
Bits 7 to 0: Error Counter Bits 15 to 8 (EC[15:8]).
Register Name: Register Description: Register Address:
BEC3 BERT Error Count Register 3 110DH + (10h x n): where n = 0 to 7, for Ports 1 to 8 6 EC22 0 5 EC21 0 4 EC20 0 3 EC19 0 2 EC18 0 1 EC17 0 0 EC16 0
Bit # Name Default
7 EC23 0
Bits 7 to 0: Error Counter Bits 23 to 16 (EC[23:16]). EC23 is the MSB of the 24-bit counter.
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DS26528 Octal T1/E1/J1 Transceiver Register Name:
Register Description: Register Address:
BLSR Bert Latched Status Register 110EH + (10h x n): where n = 0 to 7, for Ports 1 to 8 2 BRA0 0 1 BRLOS 0 0 BSYNC 0
Bit # 7 6 5 4 3 Name BBED BBCO BEC0 BRA1 Default 0 0 0 0 0 All bits in this register are latched and can create interrupts.
Bit 6: BERT Bit Error Detected (BED) Event (BBED). A latched bit, which is set when a bit error is detected. The receive BERT must be in synchronization for it to detect bit errors. Bit 5: BERT Bit Counter Overflow Event (BBCO). A latched bit, which is set when the 32-bit BERT Bit Counter (BBC) overflows. Bit 4: BERT Error Counter Overflow (BECO) Event (BECO). A latched bit, which is set when the 24-bit BERT Error Counter (BEC) overflows. Bit 3: BERT Receive All-Ones Condition (BRA1). A latched bit, which is set when 32 consecutive ones are received. Bit 2: BERT Receive All-Zeros Condition (BRA0). A latched bit, which is set when 32 consecutive zeros are received. Bit 1: BERT Receive Loss Of Synchronization Condition (BRLOS). A latched bit which is set whenever the receive BERT begins searching for a pattern. Bit 0: BERT in Synchronization Condition (BSYNC). Will be set when the incoming pattern matches for 32 consecutive bit positions.
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DS26528 Octal T1/E1/J1 Transceiver
Register Name: Register Description: Register Address:
BSIM BERT Status Interrupt Mask Register 110FH + (10h x n): where n = 0 to 7, for Ports 1 to 8 6 BBED 0 5 BBCO 0 4 BEC0 0 3 BRA1 0 2 BRA0 0 1 BRLOS 0 0 BSYNC 0
Bit # Name Default
7 0
Bit 6 : Bit Error Detected Event (BBED). 0 = interrupt masked 1 = interrupt enabled Bit 5 : BERT Bit Counter Overflow Event (BBCO). 0 = interrupt masked 1 = interrupt enabled Bit 4 : BERT Error Counter Overflow Event (BECO). 0 = interrupt masked 1 = interrupt enabled Bit 3 : Receive All Ones Condition (BRA1). 0 = interrupt masked 1 = interrupt enabled - interrupts on rising and falling edges Bit 2 : Receive All Zeros Condition (BRA0). 0 = interrupt masked 1 = interrupt enabled - interrupts on rising and falling edges Bit 1 : Receive Loss Of Synchronization Condition (BRLOS) 0 = interrupt masked 1 = interrupt enabled - interrupts on rising and falling edges Bit 0 : BERT in Synchronization Condition (BSYNC). 0 = interrupt masked 1 = interrupt enabled - interrupts on rising and falling edges
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DS26528 Octal T1/E1/J1 Transceiver
11.
FUNCTIONAL TIMING
11.1 T1 Receiver Functional Timing Diagrams Figure 11-1. T1 Receive Side D4 Timing
FRAME# RFSYNC RSYNC 1 RSYNC 2 RSYNC
3
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
Notes: 1. RSYNC in the frame mode (RIOCR.0 = 0) and doublewide frame sync is not enabled (RIOCR.1 = 0) 2. RSYNC in the frame mode (RIOCR.0 = 0) and doublewide frame sync is enabled (RIOCR.1 = 1) 3. RSYNC in the multiframe mode (RIOCR.0 = 1)
Figure 11-3. T1 Receive Side ESF Timing
FRAME# RSYNC
1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5
RFSYNC RSYNC RSYNC
2 3
Notes: 1. RSYNC in frame mode (RIOCR.0 = 0) and doublewide frame sync is not enabled (RIOCR.1 = 0) 2. RSYNC in frame mode (RIOCR.0 = 0) and doublewide frame sync is enabled (RIOCR.1 = 1) 3. RSYNC in multiframe mode (RIOCR.0 = 1)
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DS26528 Octal T1/E1/J1 Transceiver
Figure 11-5. T1 Receive Side Boundary Timing (elastic store disabled)
RCLK
CHANNEL 23 CHANNEL 24
LSB MSB LSB
CHANNEL 1
RSER RSYNC RFSYNC RSIG RCHCLK RCHBLK1
F
MSB
CHANNEL 23 A B C/A D/B
CHANNEL 24 A B C/A D/B
CHANNEL 1 A
Notes: 1. RCHBLK is programmed to block channel 24
Figure 11-7. T1 Receive Side 1.544MHz Boundary Timing (e-store enabled)
RSYSCLK
CHANNEL 23 CHANNEL 24
LSB MSB LSB
CHANNEL 1
RSER RSYNC1 RMSYNC RSYNC2 RSIG RCHCLK RCHBLK
3
F
MSB
CHANNEL 23 A B C/A D/B
CHANNEL 24 A B C/A D/B
CHANNEL 1 A
Notes: 1. RSYNC is in the output mode (RIOCR.2 = 0) 2. RSYNC is in the input mode (RIOCR.2 = 1) 3. RCHBLK is programmed to block channel 24
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DS26528 Octal T1/E1/J1 Transceiver
Figure 11-9. T1 Receive Side 2.048MHz Boundary Timing (e-store enabled)
RSYSCLK RSER RSYNC
1 CHANNEL 31
LSB MSB
CHANNEL 32
LSB
CHANNEL 1
2
RMSYNC
RSYNC
3 CHANNEL 31 B C/A D/B CHANNEL 32 B C/A D/B CHANNEL 1
RSIG RCHCLK RCHBLK
4
A
A
Notes: 1. RSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 are forced to one 2. RSYNC is in the output mode (RIOCR.2 = 0) 3. RSYNC is in the input mode (RIOCR.2 = 1) 4. RCHBLK is programmed to block channel 1 5. The F-Bit position is passed through the receive side elastic store
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DS26528 Octal T1/E1/J1 Transceiver
Figure 11-11. T1 Receive Side Interleave Bus Operation, BYTE Mode
RSYNC RSER1 RSIG1 RSER2 RSIG2 RSER3 RSIG3
FR1 CH 32 FR1 CH132 FR2 CH32 FR2 CH32
FR4 Ch32 FR4 Ch32 FR5 Ch32 FR5 Ch32
FR0 CH1 FR0 CH1 FR0 CH1 FR0 CH1
FR0 Ch1 FR0 Ch1 FR1 Ch1 FR1 Ch1
FR1 CH1 FR1 CH1 FR2 CH1 FR2 CH1
FR4 Ch1 FR4 Ch1 FR5 Ch1 FR5 Ch1
FR0 CH2 FR0 CH2 FR0 CH2 FR0 CH2
FR0 Ch2 FR0 Ch2 FR1 Ch2 FR1 Ch2
FR1 CH2 FR1 CH2 FR2 CH2 FR2 CH2
FR4 Ch2 FR4 Ch2 FR5 Ch2 FR5 Ch2
FR3 CH32 FR3 CH32
FR6 Ch32 FR6 Ch32 FR7 Ch32 FR7 Ch32
FR1 CH1 FR1 CH1
FR2 Ch1 FR2 Ch1 FR3 Ch1 FR3 Ch1
FR3 CH1 FR3 CH1
FR6 Ch1 FR6 Ch1 FR7 Ch1 FR7 Ch1
FR1 CH2 FR1 CH2
FR2 Ch2 FR2 Ch2 FR3 Ch2 FR3 Ch2
FR3 CH2 FR3 CH2
FR6 Ch2 FR6 Ch2 FR7 Ch2 FR7 Ch2
BIT DETAIL
SYSCLK RSYNC4
Framer 3, Channel 32 Framer 0, Channel 1
LSB MSB LSB MSB
Framer 1, Channel 1
LSB MSB
RSER
Framer 3, Channel 32
Framer 0, Channel 1 A B C/A D/B
Framer 1, Channel 1 A B C/A D/B A B
RSIG
A
B
C/A D/B
Notes: 1. 4.096 MHz bus configuration. 2. 8.192 MHz bus configuration. 3. 16.384 MHz bus configuration. 4. RSYNC is in the input mode (RIOCR.2 = 0). 5. Shows system implementation with multiple DS26528 cores driving the backplane. 6. Though not shown, RCHCLK continues to mark the channel LSB for the framers active period. 7. Though not shown, RCHBLK continues to mark the blocked channels for the framers active period.
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DS26528 Octal T1/E1/J1 Transceiver
Figure 11-13. T1 Receive Side Interleave Bus Operation, FRAME Mode
RSYNC RSER1 RSIG1 RSER2 RSIG2 RSER3 RSIG3
FR1 CH1-32 FR1 CH1-32 FR2 CH1-32 FR2 CH1-32
FR4 Ch1-32 FR4 Ch1-32 FR5 Ch1-32 FR5 Ch1-32
FR0 CH1-32 FR0 CH1-32
FR1 CH1-32 FR1 CH1-32 FR3 CH1-32
FR0 CH1-32 FR0 CH1-32 FR0 CH1-32 FR1 CH1-32
FR1 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR2 CH1-32 FR3 CH1-32
FR4 Ch1-32 FR4 Ch1-32 FR5 Ch1-32 FR5 Ch1-32 FR6 Ch1-32 FR6 Ch1-32 FR7 Ch1-32 FR7 Ch1-32
FR3 CH1-32 FR0 CH1-32 FR3 CH1-32
FR6 Ch1-32 FR6 Ch1-32
FR1 CH1-32 FR2 CH1-32 FR1 CH1-32
FR2 Ch1-32 FR2 Ch1-32 FR3 Ch1-32 FR3 Ch1-32
FR0 CH1-32
FR1 Ch1-32 FR1 Ch1-32
FR2 CH1-32 FR3 CH1-32
FR4 Ch1-32 FR4 Ch1-32 FR5 Ch1-32 FR5 Ch1-32 FR6 Ch1-32 FR6 Ch1-32 FR7 Ch1-32 FR7 Ch1-32
FR0 CH1-32 FR1 CH1-32
FR0 Ch1-32 FR0 Ch1-32 FR1 Ch1-32 FR1 Ch1-32 FR2 Ch1-32 FR2 Ch1-32 FR3 Ch1-32 FR3 Ch1-32
FR7 FR0 Ch1-32 Ch1-32 FR7 Ch1-32 FR0 Ch1-32
BIT DETAIL
SYSCLK RSYNC4
Framer 3, Channel 32 Framer 0, Channel 1
LSB MSB LSB MSB
Framer 0, Channel 2
LSB MSB
RSER
Framer 3, Channel 32
Framer 0, Channel 1 A B C/A D/B
Framer 0, Channel 2 A B C/A D/B A B
RSIG
A
B
C/A D/B
Notes: 1. 4.096 MHz bus configuration. 2. 8.192 MHz bus configuration. 3. 16.384 MHz bus configuration. 4. RSYNC is in the input mode (RIOCR.2 = 0). 5. Shows system implementation with multiple DS26528 cores driving the backplane. 6. Though not shown, RCHCLK continues to mark the channel LSB for the framers active period. 7. Though not shown, RCHBLK continues to mark the blocked channels for the framers active period.
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DS26528 Octal T1/E1/J1 Transceiver
11.2 T1 Transmitter Functional Timing Diagrams Figure 11-15. T1 Transmit Side D4 Timing
FRAME# TSYNC
1
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
TSSYNC TSYNC TSYNC
2 3
Notes: 1. TSYNC in the frame mode (TIOCR.0 = 0) and doublewide frame sync is not enabled (TIOCR.1 = 0) 2. TSYNC in the frame mode (TIOCR.0 = 0) and doublewide frame sync is enabled (TIOCR.1 = 1) 3. TSYNC in the multiframe mode (TIOCR.0 = 1)
Figure 11-17. T1 Transmit Side ESF Timing
FRAME# TSYNC1 TSSYNC TSYNC
2 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5
TSYNC
Notes: 1. TSYNC in frame mode (TIOCR.0 = 0) and doublewide frame sync is not enabled (TIOCR.1 = 0) 2. TSYNC in frame mode (TIOCR.0 = 0) and doublewide frame sync is enabled (TIOCR.1 = 1) 3. TSYNC in multiframe mode (TIOCR.0 = 1)
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DS26528 Octal T1/E1/J1 Transceiver
Figure 11-19. T1 Transmit Side Boundary Timing (e-store disabled)
TCLK
CHANNEL 1 CHANNEL 2
LSB MSB LSB MSB
TSER TSYNC1 TSYNC2
LSB
F
MSB
CHANNEL 1
CHANNEL 2
C/A D/B A B C/A D/B
TSIG TCHCLK TCHBLK 3
D/B
A
B
Notes: 1. TSYNC is in the output mode (TIOCR.2 = 1) 2. TSYNC is in the input mode (TIOCR.2 = 0) 3. TCHBLK is programmed to block channel 2
Figure 11-21. T1 Transmit Side 1.544MHz Boundary Timing (e-store enabled)
TSYSCLK
CHANNEL 23 CHANNEL 24
LSB MSB LSB F MSB
CHANNEL 1
TSER TSSYNC
CHANNEL 23
CHANNEL 24
C/A D/B A B C/A D/B
CHANNEL 1
A
TSIG TCHCLK TCHBLK 1
A
B
Notes: 1. TCHBLK is programmed to block channel 24
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DS26528 Octal T1/E1/J1 Transceiver
Figure 11-23. T1 Transmit Side 2.048MHz Boundary Timing (e-store enabled)
TSYSCLK
CHANNEL 31 CHANNEL 32
LSB MSB LSB
CHANNEL 1
TSER
1
F
4
TSSYNC
CHANNEL 31 CHANNEL 32
C/A D/B A B C/A D/B
CHANNEL 1
A
TSIG TCHCLK TCHBLK 2
A
B
Notes: 1. TSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 is ignored 2. TCHBLK is programmed to block channels 31 and 1 3. The F-bit position for the T1 frame is sampled and passed through the transmit side elastic store into the MSB bit position of channel 1. (normally the transmit side formatter overwrites the F-bit position unless the formatter is programmed to passthrough the F-bit position)
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DS26528 Octal T1/E1/J1 Transceiver
Figure 11-25. T1 Transmit Side Interleave Bus Operation, BYTE Mode
TSYNC TSER1 TSIG1 TSER2 TSIG2 TSER3 TSIG3
FR1 CH 32 FR1 CH132 FR2 CH32 FR2 CH32
FR4 Ch32 FR4 Ch32 FR5 Ch32 FR5 Ch32
FR0 CH1 FR0 CH1 FR0 CH1 FR0 CH1
FR0 Ch1 FR0 Ch1 FR1 Ch1 FR1 Ch1
FR1 CH1 FR1 CH1 FR2 CH1 FR2 CH1
FR4 Ch1 FR4 Ch1 FR5 Ch1 FR5 Ch1
FR0 CH2 FR0 CH2 FR0 CH2 FR0 CH2
FR0 Ch2 FR0 Ch2 FR1 Ch2 FR1 Ch2
FR1 CH2 FR1 CH2 FR2 CH2 FR2 CH2
FR4 Ch2 FR4 Ch2 FR5 Ch2 FR5 Ch2
FR3 CH32 FR3 CH32
FR6 Ch32 FR6 Ch32 FR7 Ch32 FR7 Ch32
FR1 CH1 FR1 CH1
FR2 Ch1 FR2 Ch1 FR3 Ch1 FR3 Ch1
FR3 CH1 FR3 CH1
FR6 Ch1 FR6 Ch1 FR7 Ch1 FR7 Ch1
FR1 CH2 FR1 CH2
FR2 Ch2 FR2 Ch2 FR3 Ch2 FR3 Ch2
FR3 CH2 FR3 CH2
FR6 Ch2 FR6 Ch2 FR7 Ch2 FR7 Ch2
BIT DETAIL
SYSCLK TSYNC4
Framer 3, Channel 32 Framer 0, Channel 1
LSB MSB LSB MSB
Framer 1, Channel 1
LSB MSB
TSER
Framer 3, Channel 32
Framer 0, Channel 1 A B C/A D/B
Framer 1, Channel 1 A B C/A D/B A B
TSIG
A
B
C/A D/B
Notes: 1. 4.096 MHz bus configuration. 2. 8.192 MHz bus configuration. 3. 16.384 MHz bus configuration. 4. TSYNC is in the input mode (TIOCR.2 = 0). 5. Though not shown, TCHCLK continues to mark the channel LSB for the framers active period. 6. Though not shown, TCHBLK continues to mark the blocked channels for the framers active period.
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DS26528 Octal T1/E1/J1 Transceiver
Figure 11-27. T1 Transmit Interleave Bus Operation, FRAME Mode
TSYNC TSER1 TSIG1 TSER2 TSIG2 TSER3 TSIG3
FR1 CH1-32 FR1 CH1-32 FR2 CH1-32 FR2 CH1-32
FR4 Ch1-32 FR4 Ch1-32 FR5 Ch1-32 FR5 Ch1-32
FR0 CH1-32 FR0 CH1-32
FR1 CH1-32 FR1 CH1-32 FR3 CH1-32
FR0 CH1-32 FR0 CH1-32 FR0 CH1-32 FR1 CH1-32
FR1 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR2 CH1-32 FR3 CH1-32
FR4 Ch1-32 FR4 Ch1-32 FR5 Ch1-32 FR5 Ch1-32 FR6 Ch1-32 FR6 Ch1-32 FR7 Ch1-32 FR7 Ch1-32
FR3 CH1-32 FR0 CH1-32 FR3 CH1-32
FR6 Ch1-32 FR6 Ch1-32
FR1 CH1-32 FR2 CH1-32 FR1 CH1-32
FR2 Ch1-32 FR2 Ch1-32 FR3 Ch1-32 FR3 Ch1-32
FR0 CH1-32
FR1 Ch1-32 FR1 Ch1-32
FR2 CH1-32 FR3 CH1-32
FR4 Ch1-32 FR4 Ch1-32 FR5 Ch1-32 FR5 Ch1-32 FR6 Ch1-32 FR6 Ch1-32 FR7 Ch1-32 FR7 Ch1-32
FR0 CH1-32 FR1 CH1-32
FR0 Ch1-32 FR0 Ch1-32 FR1 Ch1-32 FR1 Ch1-32 FR2 Ch1-32 FR2 Ch1-32 FR3 Ch1-32 FR3 Ch1-32
FR7 FR0 Ch1-32 Ch1-32 FR7 Ch1-32 FR0 Ch1-32
BIT DETAIL
SYSCLK TSYNC4
Framer 3, Channel 32 Framer 0, Channel 1
LSB MSB LSB MSB
Framer 0, Channel 2
LSB MSB
TSER
Framer 3, Channel 32
Framer 0, Channel 1 A B C/A D/B
Framer 0, Channel 2 A B C/A D/B A B
TSIG
A
B
C/A D/B
Notes: 1. 4.096 MHz bus configuration. 2. 8.192 MHz bus configuration. 3. 16.384 MHz bus configuration. 4. TSYNC is in the input mode (TIOCR.2 = 0). 5. Though not shown, TCHCLK continues to mark the channel LSB for the framers active period. 6. Though not shown, TCHBLK continues to mark the blocked channels for the framers active period.
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DS26528 Octal T1/E1/J1 Transceiver
11.3 E1 Receiver Functional Timing Diagrams Figure 11-29. E1 Receive Side Timing
Notes:
FRAME# RFSYNC RSYNC 1 RSYNC 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
1. RSYNC in frame mode (RIOCR.0 = 0) 2. RSYNC in multiframe mode (RIOCR.0 = 1) 3. This diagram assumes the CAS MF begins in the RAF frame
Figure 11-31. E1 Receive Side Boundary Timing (elastic store disabled)
RCLK
CHANNEL 32 CHANNEL 1
LSB
CHANNEL 2
RSER RSYNC RFSYNC
CHANNEL 32
Si
1
A
Sa4 Sa5 Sa6 Sa7 Sa8 MSB
CHANNEL 1 C D
Note 3
RSIG RCHCLK RCHBLK
1
A
B
CHANNEL 2 A B
Notes: 1. RCHBLK is programmed to block channel 1 2. Shown is a RNAF frame boundary 3. RSIG normally contains the CAS multiframe alignment nibble (0000) in channel 1
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DS26528 Octal T1/E1/J1 Transceiver
Figure 11-33. E1 Receive Side 1.544MHz Boundary Timing (e-store enabled)
RSYSCLK
CHANNEL 23/31 CHANNEL 24/32
LSB
CHANNEL 1/2
RSER
1
LSB MSB
F
MSB
RSYNC2 RMSYNC RSYNC
3
RCHCLK RCHBLK
4
Notes: 1. Data from the E1 channels 1. 5. 9, 13, 17, 21, 25, and 29 is dropped (channel 2 from the E1 link is (mapped to channel 1 of the T1 link, etc.) and the F-bit position is added (forced to one) 2. RSYNC in the output mode (RIOCR.2 = 0) 3. RSYNC in the input mode (RIOCR.2 = 1) 4. RCHBLK is programmed to block channel 24
Figure 11-35. E1 Receive Side 2.048MHz Boundary Timing (e-store enabled)
Notes: 1. RSYNC is in the output mode (RIOCR.2 = 0)
RSYSCLK
CHANNEL 31 CHANNEL 32
LSB MSB LSB MSB
CHANNEL 1
RSER RSYNC1 RMSYNC
RSYNC
2
RSIG RCHCLK RCHBLK
3
A
CHANNEL 31 C B D
A
CHANNEL 32 C B D
CHANNEL 1
Note 4
2. RSYNC is in the input mode (RIOCR.2 = 1) 3. RCHBLK is programmed to block channel 1 4. RSIG normally contains the CAS multiframe alignment nibble (0000) in Channel 1
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DS26528 Octal T1/E1/J1 Transceiver
11.4 E1 Transmitter Functional Timing Diagrams Figure 11-37. E1 Transmit Side Timing
FRAME# TSYNC
1
14 15 16 1
2
3
4
56
7
8
9 10 11 12 13 14 15 16 1
2
3
4
5
6
7
8
9 10
TSSYNC TSYNC
2
Notes: 1. TSYNC in frame mode (TIOCR.0 = 0) 2. TSYNC in multiframe mode (TIOCR.0 = 1) 3. This diagram assumes both the CAS MF and the CRC4 MF begin with the TAF frame
Figure 11-39. E1 Transmit Side Boundary Timing (elastic store disabled)
Notes:
TCLK
CHANNEL 1 CHANNEL 2
LSB MSB
TSER TSYNC1 TSYNC2
LSB
Si
1
A Sa4 Sa5 Sa6 Sa7 Sa8 MSB
CHANNEL 1
CHANNEL 2
A B C D
TSIG TCHCLK TCHBLK 3
D
1. TSYNC is in the output mode (TIOCR.2 = 1) 2. TSYNC is in the input mode (TIOCR.2 = 0) 3. TCHBLK is programmed to block channel 2 4. The signaling data at TSIG during channel 1 is normally overwritten in the transmit formatter with the CAS MF alignment nibble (0000) 5. Shown is a TNAF frame boundary
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Figure 11-41. E1 Transmit Side 1.544MHz Boundary Timing (e-store enabled)
TSYSCLK
CHANNEL 23 CHANNEL 24
LSB MSB LSB F MSB
CHANNEL 1
TSER
1
TSSYNC TCHCLK TCHBLK
2
Notes: 1. The F bit position in the TSER data is ignored 2. TCHBLK is programmed to block channel 24
Figure 11-43. E1 Transmit Side 2.048MHz Boundary Timing (e-store enabled)
TSYSCLK
CHANNEL 31 CHANNEL 32
LSB MSB LSB MSB
CHANNEL 1
TSER
TSYNC
1
TSIG TCHCLK TCHBLK
2
A
CHANNEL 31 C B D
A
CHANNEL 32 C B D
CHANNEL 1
Notes: 1. TSYNC is in the input mode (TIOCR.2 = 0) 2. TCHBLK is programmed to block channel 1
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Figure 11-45. E1 G.802 Timing
TS # RSYNC TSYNC RCHCLK TCHCLK RCHBLK TCHBLK
31 32 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2
RCLK / RSYSCLK TCLK / TSYSCLK CHANNEL 25 RSER / TSER RCHCLK / TCHCLK RCHBLK / TCHBLK
LSB MSB
CHANNEL 26
NOTES: RCHBLK or TCHBLK programmed to pulse high during time slots 1 through 15, 17 through 25, and bit 1 of time slot 26
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12.
OPERATING PARAMETERS
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Lead with Respect to VSS (except VDD)....................................................-0.3V to +5.5V Supply Voltage (VDD) Range with Respect to VSS....................................................................-0.3V to +3.63V Operating Temperature Range for DS26528.............................................................................0C to +70C Operating Temperature Range for DS26528N........................................................................-40C to +85C Storage TemperatureRange.............................................................................................-55C to +125C Soldering Temperature.................................................................See IPC/JEDEC J-STD-020A Specification
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA = -40C to +85C for DS26528N.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Logic 1 Logic 0 Supply
VIH VIL VDD
2.0 -0.3 3.135 3.3
5.5 +0.8 3.465
V V V
CAPACITANCE
(TA = +25C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance Output Capacitance
CIN COUT
7 7
pF pF
RECOMMENDED DC OPERATING CONDITIONS
(VDD = 3.135V to 3.465V, TA = -40C to +85C.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Supply Current at 3.3V Input Leakage Pullup Pin Input Leakage Tri-State Output Leakage Output Voltage (Io = -1.6mA) Output Voltage (Io = +0.4mA)
IDD IIL IILP IOL VOH VOL -10.0 -500.0 -10.0 2.4
510
875 +10.0 +10.0 +10.0
mA A A A V
1, 2 3
0.4
V
Note 1: Note 2: Note 3:
RCLK1-n = TCLK1-n = 2.048MHz. Max power dissipation is measured with all ports transmitting an all-ones data pattern with a transmitter load of 100W. Pullup pins include DIGIOEN, JTRST, JTMS, and JTDI.
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THERMAL CHARACTERISTICS
PARAMETER MIN TYP MAX UNITS NOTES
Ambient Temperature Junction Temperature Theta-JA (qJA) in Still Air for 256-Pin TE-CSBGA
Note 1: Note 2:
-40
+85 +125 +17.5
C C C/W
1
2
The package is mounted on a four-layer JEDEC standard test board. Theta-JA (qJA) is the junction-to-ambient thermal resistance, when the package is mounted on a four-layer JEDEC standard test board.
12.1 Line Interface Characteristics Table 12-1. Transmitter Characteristics
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Output Mark Amplitude
Vm
E1 75W E1 120W T1 100W J1 110W
2.13 2.70 2.40 2.40 -0.3 -1
2.37 3.00 3.00 3.00
2.61 3.30 3.60 3.60 +0.3 +1
V
Output Zero Amplitude Transmit Amplitude Variation with Supply
Vs
V %
1
Table 12-2. Reciever Characteristics
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Cable Attenuation Allowable Zeros Before Loss
Attn 192 192 2048 24 192 192
43
dB 1
Allowable Ones Before Loss
2
Note 1: Note 2:
192 Zeros for T1 and T1.231 Specification Compliance. 192 Zeros for E1 and G.775 Specification Compliance. 2048 Zeros for ETSI 300 233 compliance. 24 ones in 192-bit period for T1.231; 192 ones for G.775; 192 ones for ETSI 300 233.
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13.
AC TIMING CHARACTERISTICS
Unless otherwise noted, all timing numbers assume 20pF test load on output signals, 40pF test load on bus signals.
13.1 Microprocessor Bus AC Characteristics Table 13-1. AC Characteristics -Microprocessor Bus Timing
(VDD = 3.3V 5%, TA = 0C to +70C for DS26528; VDD = 3.3V 5%, TA = -40C to +85C for DS26528N.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Setup Time for A[7:0] Valid to CSB Active Setup Time for CSB Active to either RDB, or WRB Active Delay Time from Either RDB or DSB Active to D:AD[7:0] Valid Hold Time from Either RDB or WRB Inactive to CSB Inactive Hold Time from CSB or RDB or DSB Inactive to D:AD[7:0] Tri-State Wait Time from WRB Active to Latch Data Data Setup Time to WRB Inactive Data Hold Time from WRB Inactive Address Hold from WRB Inactive Write Access to Subsequent Write/Read Access Delay Time
Note 1:
t1 t2 t3 t4 t5
t6
0 0 125 0 5 40 10 2 0 80 20
ns ns ns ns ns ns ns ns ns ns 1 1
t7 t8 t9 t10
If supplying a 1.544MHz MCLK, the FREQSEL bit must be set to meet this timing.
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Figure 13-1. Intel Bus Read Timing (BTS = 0)
t9
ADDR[11:0] DATA[7:0]
WRB
Address Valid
Data Valid t5
t1
CSB
t2 t3 t4 t10
RDB
Figure 13-3. Intel Bus Write Timing (BTS = 0)
t9
ADDR[11:0] DATA[7:0]
Address Valid
t7
t8
RDB
t1
CSB
t2 t6 t4 t10
WRB
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Figure 13-5. Motorola Bus Read Timing (BTS = 1)
t9
ADDR[12:0] DATA[7:0]
RWB
Address Valid
Data Valid t5
t1
CSB
t2 t3 t4 t10
DSB
Figure 13-7. Motorola Bus Write Timing (BTS = 1)
t9
ADDR[11:0] DATA[7:0]
Address Valid
t7
t8
RWB
t1
CSB
t2 t6 t4 t10
DSB
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Table 13-2. Receiver AC Characteristics
(VDD = 3.3V 5%, TA = -40C to +85C.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
648 RCLK Period tCP 488 RCLK Pulse Width tCH tCL RSYSCLK Period tSP 60 RSYSCLK Pulse Width RSYNC Setup to RSYSCLK Falling RSYNC Pulse Width RTIP:RRING Setup to RCLK Falling RTIP:RRING Hold From RCLK Falling Delay RCLK to RSER, RSIG Valid Delay RCLK to RCHCLK, RSYNC, RCHBLK, RFSYNC Delay RSYSCLK to RSER, RSIG Valid Delay RSYSCLK to RCHCLK, RCHBLK, RMSYNC, RSYNC
Note 1: Note 2: Note 3: Note 4:
1 ns 2 ns
125 125 60 648 ns 488 ns tSH - 5 ns ns ns ns 50 50 50 50 ns ns ns ns 4 30 30 20 50 20 20 3
tSH tSL tSU tPW tSU tHD tD1 tD2 tD3 tD4
T1 Mode. E1 Mode. RSYSCLK = 1.544MHz. RSYSCLK = 2.048MHz.
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Figure 13-9. Receive Framer Timing--Backplane (T1 Mode)
RCLK t D1 RSER / RSIG
t D2
F Bit
RCHCLK t D2 RCHBLK t D2 RFSYNC / RMSYNC t D2 RSYNC 1
Notes: 1. RSYNC is in the output mode 2. No Relationship between RCHCLK and RCHBLK and other signals is implied
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Figure 13-11. Receive Side Timing, Elastic Store Enabled (T1 Mode)
t SL t SH t SP
RSYSCLK
t D3
RSER / RSIG
t D4
SEE NOTE 3
RCHCLK
t D4
RCHBLK
t D4
RMSYNC RSYNC 1 2
t D4 t HD t SU
RSYNC
Notes: 1. RSYNC is in the output mode 2. RSYNC is in the input mode 3. F-BIT when RIOCR.4 = 0, MSB of TS0 when RIOCR.4 = 1
Figure 13-13. Receive Framer Timing--Line Side
t CL RCLK t SU RTIP, RRING t HD t CH
t CP
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Table 13-3. Transmit AC Characteristics
(VDD = 3.3V 5%, TA = -40C to +85C.)
PARAMETER SYMBOL tCP tCP tCH tCL tSP tSP tSH tSL MIN TYP 648 488 MAX UNITS NOTES 1 2
TCLK Period TCLK Pulse Width TSYSCLK Period TSYSCLK Pulse Width TSYNC or TSSYNCIO Setup to TCLK or TSYSCLK falling TSYNC or TSSYNCIO Pulse Width TSSYNCIO Pulse Width TSER, TSIG, Setup to TCLK, TSYSCLK Falling TSER, TSIG, Hold from TCLK, TSYSCLK Falling Delay TCLK to TCHBLK, TCHCLK, TSYNC Delay TSYSCLK to TCHCLK, TCHBLK Delay TCLK to TTIP, TRING Delay BPCLK to TSSYNCIO
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7:
ns ns
125 125 60 60 30 30 20 50 488 244 122 61 20 20
648 448
ns ns tCH - 5 or tSH - 5 ns ns ns ns ns 50 50 50 5 ns ns ns ns
3 4
tSU tPW tPW tSU tHD tD2 tD3 tD4 tD5
5 6, 7
6
T1 Mode. E1 Mode. RSYSCLK = 1.544MHz. RSYSCLK = 2.048MHz. TSSYNCIO configured as an Input (GTCR2.1 = 0) TSSYNCIO configured as an Output (GTCR2.1 = 1) Varies depending on the frequency of BPCLK
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Figure 13-15. Transmit Formatter Timing--Backplane
t CP t CL TCLK t D1 TESO t SU TSER / TSIG t D2 TCHCLK TCHBLK t D2 TSYNC1 t SU TSYNC2
Notes: 1. TSYNC is in the output mode 2. TSYNC is in the input mode 3. TSER is sampled on the falling edge of TCLK when the transmit side elastic store is disabled. 4. TCHCLK and TCHBLK are synchronous with TCLK when the transmit side elastic store is disabled. 5. No relationship between TCHCLK and TCHBLK and the other signals is implied.
t CH
t HD
t D2
t HD
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Figure 13-17. Transmit Formatter Timing, Elastic Store Enabled
t SP t SL TSYSCLK t SU TSER t D3 TCHCLK t D3 TCHBLK t SU TSSYNC
Notes: 1. TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled. 2. TCHCLK and TCHBLK are synchronous with TSYSCLK when the transmit side elastic store is enabled.
t SH
t HD
t HD
Figure 13-19. BPCLK Timing
B PC LK T SS YN C IO 1 t D5
N otes: 1. TS S Y N C IO is configured as an O utput (G TC R 2.TS S Y N IO S E L = 1)
Figure 13-20. Transmit Formatter Timing--Line Side
t CP t CL TCLK t CH
TTIP, TRING t D3
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13.2 JTAG Interface Timing
(VDD = 3.3V 5%, TA = -40C to +85C.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
JTCLK Clock Period JTCLK Clock High:Low Time JTCLK to JTDI, JTMS Setup Time JTCLK to JTDI, JTMS Hold Time JTCLK to JTDO Delay JTCLK to JTDO HIZ Delay
JTRST Width Low Time
Note 1:
t1 t2:t3 t4 t5 t6 t7 t8 50 5 2 2 2 100
1000 500
ns ns ns ns 50 50 ns ns ns 1
Clock can be stopped high or low.
Figure 13-22. JTAG Interface Timing Diagram
t1 t2 JTCLK t3
t4 JTDI, JTMS, JTRST t6
t5
t7
JTD0
JTRST
t8
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13.3 System Clock AC Characteristics
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
1.544 REF_CLK Frequency 2.048 REF_CLK Duty Cycle Gapped Clock Frequency Gapped Clock Duty Cycle
Note 1:
MHz 40 43 40 45 60 60 60 % MHz % 1
The gapped clock is output on the RCHCLK pin when RESCR.6=1.
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14.
JTAG-BOUNDARY SCAN AND TEST ACCESS PORT
The DS26528 IEEE 1149.1 design supports the standard instruction codes SAMPLE:PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. See Table 14-1. The DS26528 contains the following as required by IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Test Access Port (TAP) TAP Controller Instruction Register Bypass Register Boundary Scan Register Device Identification Register The Test Access Port has the necessary interface pins; JTRST, JTCLK, JTMS, JTDI, and JTDO. See the pin descriptions for details.
Figure 14-1. JTAG Functional Block Diagram
BOUNDRY SCAN REGISTER IDENTIFICATION REGISTER BYPASS REGISTER INSTRUCTION REGISTER
MUX
TEST ACCESS PORT CONTROLLER
Vdd
10K
SELECT OUTPUT ENABLE
Vdd
10K
Vdd
10K
JTDI
JTMS
JTCLK
JTRST
JTDO
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TAP CONTROLLER STATE MACHINE
The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. See Figure 14-3.
Test-Logic-Reset
Upon power up, the TAP Controller will be in the Test-Logic-Reset state. The Instruction register will contain the IDCODE instruction. All system logic of the device will operate normally.
Run-Test-Idle
The Run-Test-Idle is used between scan operations or during specific tests. The Instruction register and test registers will remain idle.
Select-DR-Scan
All test registers retain their previous state. With JTMS LOW, a rising edge of JTCLK moves the controller into the Capture-DR state and will initiate a scan sequence. JTMS HIGH during a rising edge on JTCLK moves the controller to the Select-IR-Scan state.
Capture-DR
Data may be parallel-loaded into the test data registers selected by the current instruction. If the instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register will remain at its current value. On the rising edge of JTCLK, the controller will go to the Shift-DR state if JTMS is LOW or it will go to the Exit1-DR state if JTMS is HIGH.
Shift-DR
The test data register selected by the current instruction will be connected between JTDI and JTDO and will shift data one stage towards its serial output on each rising edge of JTCLK. If a test register selected by the current instruction is not placed in the serial path, it will maintain its previous state.
Exit1-DR
While in this state, a rising edge on JTCLK will put the controller in the Update-DR state, which terminates the scanning process, if JTMS is HIGH. A rising edge on JTCLK with JTMS LOW will put the controller in the PauseDR state.
Pause-DR
Shifting of the test registers is halted while in this state. All test registers selected by the current instruction will retain their previous state. The controller will remain in this state while JTMS is LOW. A rising edge on JTCLK with JTMS HIGH will put the controller in the Exit2-DR state.
Exit2-DR
A rising edge on JTCLK with JTMS HIGH while in this state will put the controller in the Update-DR state and terminate the scanning process. A rising edge on JTCLK with JTMS LOW will enter the Shift-DR state.
Update-DR
A falling edge on JTCLK while in the Update-DR state will latch the data from the shift register path of the test registers into the data output latches. This prevents changes at the parallel output due to changes in the shift register.
Select-IR-Scan
All test registers retain their previous state. The instruction register will remain unchanged during this state. With JTMS LOW, a rising edge on JTCLK moves the controller into the Capture-IR state and will initiate a scan sequence for the instruction register. JTMS HIGH during a rising edge on JTCLK puts the controller back into the Test-Logic-Reset state.
Capture-IR
The Capture-IR state is used to load the shift register in the instruction register with a fixed value. This value is loaded on the rising edge of JTCLK. If JTMS is HIGH on the rising edge of JTCLK, the controller will enter the Exit1-IR state. If JTMS is LOW on the rising edge of JTCLK, the controller will enter the Shift-IR state.
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Shift-IR
In this state, the shift register in the instruction register is connected between JTDI and JTDO and shifts data one stage for every rising edge of JTCLK towards the serial output. The parallel register, as well as all test registers, remains at their previous states. A rising edge on JTCLK with JTMS HIGH will move the controller to the Exit1-IR state. A rising edge on JTCLK with JTMS LOW will keep the controller in the Shift-IR state while moving data one stage thorough the instruction shift register.
Exit1-IR
A rising edge on JTCLK with JTMS LOW will put the controller in the Pause-IR state. If JTMS is HIGH on the rising edge of JTCLK, the controller will enter the Update-IR state and terminate the scanning process.
Pause-IR
Shifting of the instruction shift register is halted temporarily. With JTMS HIGH, a rising edge on JTCLK will put the controller in the Exit2-IR state. The controller will remain in the Pause-IR state if JTMS is LOW during a rising edge on JTCLK.
Exit2-IR
A rising edge on JTCLK with JTMS LOW will put the controller in the Update-IR state. The controller will loop back to Shift-IR if JTMS is HIGH during a rising edge of JTCLK in this state.
Update-IR
The instruction code shifted into the instruction shift register is latched into the parallel output on the falling edge of JTCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising edge on JTCLK with JTMS LOW, will put the controller in the Run-Test-Idle state. With JTMS HIGH, the controller will enter the Select-DR-Scan state.
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Figure 14-3. Tap Controller State Diagram
1 Test Logic Reset 0 Run Test/ Idle 1 Select DR-Scan 0 1 Capture DR 0 Shift DR 1 Exit DR 0 Pause DR 1 0 Exit2 DR 1 Update DR 1 0 0 0 1 0 1 1 Select IR-Scan 0 Capture IR 0 Shift IR 1 Exit IR 0 Pause IR 1 Exit2 IR 1 Update IR 1 0 0 1 0 1
0
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14.1 Instruction Register
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register will be connected between JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS LOW will shift the data one stage towards the serial output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with JTMS HIGH will move the controller to the Update-IR state. The falling edge of that same JTCLK will latch the data in the instruction shift register to the instruction parallel output. Instructions supported by the DS26528 and its respective operational binary codes are shown in Table 14-1.
Table 14-1. Instruction Codes for IEEE 1149.1 Architecture
INSTRUCTION SELECTED REGISTER INSTRUCTION CODES
SAMPLE:PRELOAD BYPASS EXTEST CLAMP HIGHZ IDCODE
Boundary Scan Bypass Boundary Scan Bypass Bypass Device Identification
010 111 000 011 100 001
SAMPLE:PRELOAD
This is a mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The digital I/Os of the device can be sampled at the boundary scan register without interfering with the normal operation of the device by using the Capture-DR state. SAMPLE:PRELOAD also allows the device to shift data into the boundary scan register via JTDI using the Shift-DR state.
BYPASS
When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO through the one-bit bypass test register. This allows data to pass from JTDI to JTDO not affecting the device's normal operation.
EXTEST
This allows testing of all interconnections to the device. When the EXTEST instruction is latched in the instruction register, the following actions occur. Once enabled via the Update-IR state, the parallel outputs of all digital output pins will be driven. The boundary scan register will be connected between JTDI and JTDO. The Capture-DR will sample all digital inputs into the boundary scan register.
CLAMP
All digital outputs of the device will output data from the boundary scan parallel output while connecting the bypass register between JTDI and JTDO. The outputs will not change during the CLAMP instruction.
HIGHZ
All digital outputs of the device will be placed in a high impedance state. The BYPASS register will be connected between JTDI and JTDO.
IDCODE
When the IDCODE instruction is latched into the parallel instruction register, the identification test register is selected. The device identification code will be loaded into the identification register on the rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially via JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register's parallel output. The ID code will always have a `1' in the LSB position. The next 11 bits identify the manufacturer's JEDEC number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version.
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14.2 JTAG ID Codes Table 14-2. ID Code Structure
DEVICE REVISION ID[31:28] DEVICE CODE ID[27:12] MANUFACTURER'S CODE ID[11:1] REQUIRED ID[0]
DS26528 DS26524
Consult factory Consult factory
0000000000110111 0000000000111001
00010100001 00010100001
1 1
14.3 Test Registers
IEEE 1149.1 requires a minimum of two test registers; the bypass register and the boundary scan register. An optional test register has been included with the DS26528 design. This test register is the identification register and is used in conjunction with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.
14.4 Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and digital I/O cells and is n bits in length. See Table 14-3 for all of the cell bit locations and definitions.
14.5 Bypass Register
This is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ instructions, which provides a short path between JTDI and JTDO.
14.6 Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.
Table 14-3. Boundary Scan Control Bits
CELL#
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
NAME
-- rser(1) -- rm_rfsync(1) rm_rfsync(1) -- rsync(1) rsync(1) -- tsig(1) tsig(1) -- tsync(1) tsync(1) tser(1) tclk(1) -- tchblk_clk(1) tchblk_clk(1)
TYPE
controlr output3 controlr output3 observe_only controlr output3 observe_only controlr output3 observe_only controlr output3 observe_only observe_only observe_only controlr output3 observe_only
CONTROL CELL
0 2
CELL#
19 20 21 22 23 24
NAME
-- rchblk_clk(2) rchblk_clk(2) -- rsig(2) rsig(2) -- rlf_ltc(2) -- al_rsigf_flos(2) -- rser(2) -- rm_rfsync(2) rm_rfsync(2) -- rsync(2) rsync(2) --
TYPE
controlr output3 observe_only controlr output3 observe_only controlr output3 controlr output3 controlr output3 controlr output3 observe_only controlr output3 observe_only controlr
CONTROL CELL
19
22
5
25 26 27
25 27 29 31
8
28 29 30
11
31 32 33 34 35
34
16
36 37
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CELL#
38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
NAME
tsig(2) tsig(2) -- tsync(2) tsync(2) tser(2) tclk(2) -- tchblk_clk(2) tchblk_clk(2) mclk -- refclkio refclkio -- bpclk a(12) a(11) a(10) digio_en a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) -- tchblk_clk(7) tchblk_clk(7) tclk(7) tser(7) -- tsync(7) tsync(7) -- tsig(7) tsig(7) --
TYPE
output3 observe_only controlr output3 observe_only observe_only observe_only controlr output3 observe_only observe_only controlr output3 observe_only controlr output3 observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only observe_only controlr output3 observe_only observe_only observe_only controlr output3 observe_only controlr output3 observe_only controlr
CONTROL CELL 37
CELL#
80 81 82
NAME
rsync(7) rsync(7) -- rm_rfsync(7) rm_rfsync(7) -- rser(7) -- al_rsigf_flos(7) -- rlf_ltc(7) -- rsig(7) rsig(7) -- rchblk_clk(7) rchblk_clk(7) -- tchblk_clk(8) tchblk_clk(8) tclk(8) tser(8) -- tsync(8) tsync(8) -- tsig(8) tsig(8) -- rsync(8) rsync(8) -- rm_rfsync(8) rm_rfsync(8) -- rser(8) -- al_rsigf_flos(8) -- rlf_ltc(8) -- rclk(8)
TYPE
output3 observe_only controlr output3 observe_only controlr output3 controlr output3 controlr output3 controlr output3 observe_only controlr output3 observe_only controlr output3 observe_only observe_only observe_only controlr output3 observe_only controlr output3 observe_only controlr output3 observe_only controlr output3 observe_only controlr output3 controlr output3 controlr output3 controlr output3
CONTROL CELL 79
40
83 84 85 86 87
82
85 87 89 91
45
88 89 90 91
49
92 93 94
52
95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110
94
97
102
105
108
68
111 112 113 114 115
111
114 116 118 120
73
116 117 118
76
119 120 121
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DS26528 Octal T1/E1/J1 Transceiver
CELL#
122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163
NAME
rclk(8) -- rclk(7) rclk(7) -- rsig(8) rsig(8) -- rchblk_clk(8) rchblk_clk(8) -- rclk(6) rclk(6) -- rclk(5) rclk(5) resetb txen_b bts rsysclk -- tssyncio tssyncio tsysclk -- rchblk_clk(6) rchblk_clk(6) -- rsig(6) rsig(6) -- rlf_ltc(6) -- al_rsigf_flos(6) -- rser(6) -- rm_rfsync(6) rm_rfsync(6) -- rsync(6) rsync(6)
TYPE
observe_only controlr output3 observe_only controlr output3 observe_only controlr output3 observe_only controlr output3 observe_only controlr output3 observe_only observe_only observe_only observe_only observe_only controlr output3 observe_only observe_only controlr output3 observe_only controlr output3 observe_only controlr output3 controlr output3 controlr output3 controlr output3 observe_only controlr output3 observe_only
CONTROL CELL
CELL#
164 165
NAME
-- tsig(6) tsig(6) -- tsync(6) tsync(6) tser(6) tclk(6) -- tchblk_clk(6) tchblk_clk(6) -- rchblk_clk(5) rchblk_clk(5) -- rsig(5) rsig(5) -- rlf_ltc(5) -- al_rsigf_flos(5) -- rser(5) -- rm_rfsync(5) rm_rfsync(5) -- rsync(5) rsync(5) -- tsig(5) tsig(5) -- tsync(5) tsync(5) tser(5) tclk(5) -- tchblk_clk(5) tchblk_clk(5) -- intb
TYPE
controlr output3 observe_only controlr output3 observe_only observe_only observe_only controlr output3 observe_only controlr output3 observe_only controlr output3 observe_only controlr output3 controlr output3 controlr output3 controlr output3 observe_only controlr output3 observe_only controlr output3 observe_only controlr output3 observe_only observe_only observe_only controlr output3 observe_only controlr output3
CONTROL CELL
164
123
166 167 168
167
126
169 170 171
129
172 173 174
172
132
175 176 177
175
135
178 179 180 181 182 183 184
178
181 183 185 187
142
185 186 187 188
146
189 190 191
190
149
192 193 194
193
152 154 156 158
195 196 197 198 199 200 201 202 203
196
201
161
204 205
204
266 of 269
DS26528 Octal T1/E1/J1 Transceiver
CELL#
206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247
NAME
d(7) d(7) d(6) d(6) d(5) d(5) d(4) d(4) d(3) d(3) d(2) d(2) d(1) d(1) -- d(0) d(0) rdb_dsb wrb_rwb csb -- tchblk_clk(4) tchblk_clk(4) tclk(4) tser(4) -- tsync(4) tsync(4) -- tsig(4) tsig(4) -- rsync(4) rsync(4) -- rm_rfsync(4) rm_rfsync(4) -- rser(4) -- al_rsigf_flos(4) --
TYPE
output3 observe_only output3 observe_only output3 observe_only output3 observe_only output3 observe_only output3 observe_only output3 observe_only controlr output3 observe_only observe_only observe_only observe_only controlr output3 observe_only observe_only observe_only controlr output3 observe_only controlr output3 observe_only controlr output3 observe_only controlr output3 observe_only controlr output3 controlr output3 controlr
CONTROL CELL 220
220 220 220 220 220 220
CELL#
248 249 250 251 252 253 254 255 256 257 258 259 260 261 262
NAME
rlf_ltc(4) -- rsig(4) rsig(4) -- rchblk_clk(4) rchblk_clk(4) -- tchblk_clk(3) tchblk_clk(3) tclk(3) tser(3) -- tsync(3) tsync(3) -- tsig(3) tsig(3) -- rsync(3) rsync(3) -- rm_rfsync(3) rm_rfsync(3) -- rser(3) -- al_rsigf_flos(3) -- rlf_ltc(3) -- rsig(3) rsig(3) -- rchblk_clk(3) rchblk_clk(3) -- rclk(4) rclk(4) -- rclk(3) rclk(3)
TYPE
output3 controlr output3 observe_only controlr output3 observe_only controlr output3 observe_only observe_only observe_only controlr output3 observe_only controlr output3 observe_only controlr output3 observe_only controlr output3 observe_only controlr output3 controlr output3 controlr output3 controlr output3 observe_only controlr output3 observe_only controlr output3 observe_only controlr output3 observe_only
CONTROL CELL 247
249
252
255
260
220
263 264 265 266 267 268
263
266
226
269 270 271 272 273
269
272 274 276 278
231
274 275 276
234
277 278 279
237
280 281 282
281
240
283 284 285
284
243 245
286 287 288 289
287
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DS26528 Octal T1/E1/J1 Transceiver
CELL#
290 291 292 293 294 295 296 297
NAME
-- rclk(2) rclk(2) -- rclk(1) rclk(1) -- rchblk_clk(1)
TYPE
controlr output3 observe_only controlr output3 observe_only controlr output3
CONTROL CELL
290
CELL#
298 299 300 301
NAME
rchblk_clk(1) -- rsig(1) rsig(1) -- rlf_ltc(1) -- al_rsigf_flos(1)
TYPE
observe_only controlr output3 observe_only controlr output3 controlr output3
CONTROL CELL
299
293
302 303 304
302 304
296
305
15.
DOCUMENT REVISION HISTORY
DESCRIPTION
REVISION
072304
New Product Release
1. 2. 3. 4. 5. 6. 7. 8. 9. Corrected the default direction of RIOCR.RSIO = 1 to show that the default direction of RSYNC is Input. Added Figure 13-3 for BPCLK and TSSYNCIO timing and updated Table 13-3. Corrected Figure 7-3 to show different relationship of TSSYNCIO depending on the operation mode (either Input or Output). Added Section 9.9.6.3 to provide more details on Sa bit support. Modified RIM7 register at address 0A6h for E1 mode document additional Sa bit support. Added E1RSAIMR (014h) for E1 mode to allow Sa bit interrupt masks. Added SABITS (06Eh) register to indicate the last valid Sa bits received. Added Sa6CODE (06Fh) register to indicate the reported Sa6 received pattern. Changed the recommended Line Interface Circuit (Figure 9-11) to match the Telecom App Note 324. Corrected the Recommended Supply Decoupling Capacitor values: changed the digital recommended value from 0.1mF to 0.01mF because the 0.01mF value was listed twice. Figure 8-1 - Added associated port number to each analog ATVDD/ATVSS and ARVDD/ARVSS pair to help clarify the recommended decoupling for these pins. Note, the pin locations did not change, and the functional description did not change, the numbers 1-8 were only added for clarification purposes. Added a note to TTIP and TRING Pin descriptions in Table 8-1 to clarify that the two pins shown should tied together (for example, pins A1 and A2 for TTIP1). Corrected the AIS (Blue Alarm) set criteria from 5 or less zeros in a 3ms window to 4 or less zeros and changed the clear criteria from 6 or more zeros in a 3ms window to 5 or more zeros. This is defined in Table 9-23. Added E1BCR1 and E1EBCR2 to Table 9-22. Added note to indicate that Transmit Open Circuit Detect and Short Circuit Detect are not functional in the CSU modes (T1 LBO 5, 6 and 7). This was added in the bit description of register LLSR Bit 1 (SCD) and Bit2 (OCD), as well as Section 9.11.2.4. Removed references to RPOS/RNEG, TPOS/TNEG and replaced them with RTIP/RRING and TTIP/TRING for clarification. Corrected the typical current draw in Section 12.
120204
10. 11.
12. 13.
14.
15.
1.
012405
2.
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DS26528 Octal T1/E1/J1 Transceiver
16.
PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.)
269 of 269
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(c) 2005 Maxim Integrated Products * Printed USA are registered trademarks of Maxim Integrated Products, Inc., and Dallas Semiconductor Corporation.

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